C Mode Register 1 (Simr1) - Renesas RX100 Series User Manual

RX13T Group
2
23.2.15 I

C Mode Register 1 (SIMR1)

Address(es): SCI1.SIMR1 0008 A029h, SCI5.SIMR1 0008 A0A9h, SCI12.SIMR1 0008 B309h
b7 b6
0 0
Value after reset:
Bit Symbol Bit Name
b0 IICM Simple I
b2, b1 — Reserved
b7 to b3 IICDL[4:0] SSDA Output Delay Select
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR are 0 (both serial transmission and reception are
disabled).
SIMR1 is used to select simple I
2
IICM Bit (Simple I C Mode Select)
In conjunction with the SMIF bit in the SCMR register, this bit selects the operating mode.
IICDL[4:0] Bits (SSDA Output Delay Select)
These bits are used to set a delay for output on the SSDAn pin relative to the falling edge of the output on the SSCLn pin.
The available delay settings range from no delay to 31 cycles, with the clock signal from the on-chip baud rate generator
as the base. The signal obtained by frequency-dividing PCLK by the divisor set in the SMR.CKS[1:0] bits is supplied as
the clock signal from the on-chip baud rate generator. Set these bits to 00000b unless operation is in simple I
2
simple I C mode, set the bits to a value in the range from 00001b to 11111b.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
IICDL[4:0] —
0 0 0 0
Description
2
C Mode Select
SMIF IICM
0
0
1
1
These bits are read as 0. The write value should be 0.
(Cycles below are of the clock signal from the on-chip baud rate
generator.)
b7
0 0 0 0 0: No output delay
0 0 0 0 1: 0 to 1 cycle
0 0 0 1 0: 1 to 2 cycles
0 0 0 1 1: 2 to 3 cycles
0 0 1 0 0: 3 to 4 cycles
0 0 1 0 1: 4 to 5 cycles
1 1 1 1 0: 29 to 30 cycles
1 1 1 1 1: 30 to 31 cycles
2
C mode and the number of delay stages for the SSDA output.
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
— IICM
0 0
0: Asynchronous mode, Multi-processor mode,
Clock synchronous mode
(in asynchronous mode, synchronous, or simple SPI mode)
2
1: Simple I C mode
0: Smart card interface mode
1: Setting prohibited.
b3
: :
R/W
1
R/W*
R/W
R/W* 1
2
C mode. In
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