Renesas RX100 Series User Manual page 273

RX13T Group
System clock
ICU.IRn
DTC transfer request
Read skip enable
DTC access
n = Vector number
Note: When request sources (vector numbers) of (1) and (2) are the same and the DTCCR.RRS bit is 1, the transfer information read for
request (2) is skipped.
Figure 16.14 Example of Operation When Transfer Information Read Skip is Executed
(Vector, Transfer Information, and Transfer Destination Data on the RAM, and Transfer Source
Data on the Peripheral Module)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
(1)
Vector read Transfer
information read
16. Data Transfer Controller (DTCb)
(2)
R W
Transfer
Data
information write
transfer
R W
R
Data Transfer
transfer information write
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