Renesas RX100 Series User Manual page 700

RX13T Group
Set 1 to ESMER.ESME
Set CR1.BFE and CF0RE
Set CR1.CF1DS[1:0] and PIBE
Set CR1.PIBS[2:0]
Set the bits for comparison in Control Field 1 of CF1CR
Set the data for comparison with Control Field 1 to
PCF1DR and SCF1DR
Set the bits for comparison in Control Field 0 of CF0CR
Set the data for comparison with Control Field 0 to CF0DR
Set 01b to TMR.TOMS[1:0]
Set TMR.TCSS[2:0], and set TCNT and TPRE
Set CR2.RTS[1:0], BCCS[1:0], and DFCS[2:0]
Set PCR.SHARPS, RXDXPS, and TXDXPS
SCI12 initialization
Set 1 to each bit in STCR
Set ICR.AEDIE, BCDIE, PIBDIE, CF1MIE, CF0MIE, and BFDIE
Figure 23.64 Sample Flowchart for Reception of a Start Frame (1)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Start
B
23. Serial Communications Interface (SCIg, SCIh)
Enable the extended serial mode control section.
Set whether to include the Break Field and Control Field 0
in the Start Frame.
Select the data for comparison with Control Field 1 and the
presence or absence of a priority interrupt bit.
Select the bit of Control Field 1 that will be the priority
interrupt bit.
Select the bits for comparison in Control Field 1.
Set the data for comparison with Control Field 1.
Select the bits for comparison in Control Field 0.
Set the data for comparison with Control Field 0.
Set Break Field low width detection mode as the operating
mode of the timer.
Set the clock source for counting and registers TCNT and
TPRE to values that suit the period for the Break Field low
width.
Set the timing of sampling for RXDX12 reception, clock for
bus collision detection, and sampling clock for the RXDX12
signal's digital filter.
Set the RXDX12 and TXDX12 pins.
Initialize SCI12 (refer to the example of a flowchart of SCI
initialization (asynchronous mode)). However, set the SCR.TE
bit to 1 and the SCR.RE bit to 0 for transmission and the
SCR.TE bit to 0 and the SCR.RE bit to 1 for reception.
Clear all flags in the STR register.
Set interrupt-enable bits as required.
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