Dtc Index Table - Renesas RX100 Series User Manual

RX13T Group
16.4.11

DTC Index Table

The DTC index table is allocated to the area where its start address is configured in the DTCIBR register.
Store the start address of transfer information table p for sequence number p in the address of DTCIBR + p × 4.
The upper 30 bits of the start address is set to the upper 30 bits of the DTC index. Set the CPUSEL bit to select either of
reading the transfer information and starting the sequence, or output an interrupt request to the CPU without starting the
sequence. For a complicated sequence that the DTC cannot handle, set the CPUSEL bit to 1 to allow the CPU to handle
such a sequence.
DTC index table base address
DTC index address = DTCIBR + sequence number × 4
Figure 16.17 DTC Index Table
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
DTC index table
Start address of transfer
information table 0 (upper 30 bits)
+4
Start address of transfer
information table 1 (upper 30 bits)
+8
0000 0000 0······0 0000 00
+ p × 4
Start address of transfer
information table p (upper 30 bits)
00
00
01
00
4 bytes
16. Data Transfer Controller (DTCb)
Transfer information table 0
Transfer information
Transfer information
Transfer information table p
Transfer information
Transfer information
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