Examples Of Dtc Usage; Normal Transfer - Renesas RX100 Series User Manual

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Examples of DTC Usage

As an example of DTC usage, its employment in the reception of 128 bytes of data by an SCI is described below.

(1) Transfer Information Setting

Set the MRA.MD[1:0] bits to 00b (normal transfer mode), the MRA.SZ[1:0] bits to 00b (byte transfer), and the

MRA.SM[1:0] bits to 00b (source address is fixed). Set the MRB.CHNE bit to 0 (chain transfer is disabled), the

MRB.DISEL bit to 0 (an interrupt request to the CPU is generated on completion of the specified number of data

transfers), and the MRB.DM[1:0] bits to 10b (DAR is incremented after data transfer). The MRB.DTS bit can be set to

any value. Set the RDR register address of the SCI in the SAR register, the start address of the RAM area for data storage

in the DAR register, and 128 (0080h) in the CRA register. The CRB register can be set to any value.

(2) DTC Vector Table Setting

The start address of the transfer information for the RXI interrupt is set in the vector table for the DTC.

(3) ICU Setting and DTC Module Activation

Set the corresponding ICU.DTCERn.DTCE bit to 1 and the ICU.IERm.IENj bit to 1.

Set the DTCST.DTCST bit to 1.

(4) SCI Setting

Enable the RXI interrupt by setting the SCR.RIE bit in the SCI to 1. If a reception error occurs during the SCI receive

operation, further reception is not performed. Accordingly, make settings so that the CPU can accept receive error

(5) DTC Transfer

Every time the reception of 1 byte by the SCI is completed, an RXI interrupt is generated to start the data transfer. The

DTC transfers the received byte from the RDR of the SCI to RAM, after which the DAR register is incremented and the

CRA register is decremented.

(6) Interrupt Handling

After 128 times of data transfers have been completed and the value in the CRA register becomes 0, an RXI interrupt

request is output to the CPU. Complete the process in the handling routine for this interrupt.

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

16. Data Transfer Controller (DTCb)

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