Execution Cycles Of The Dtc; Dtc Bus Mastership Release Timing - Renesas RX100 Series User Manual

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Execution Cycles of the DTC

Table 16.9 lists the execution cycles of single data transfer of the DTC.

For the order of the execution states, refer to section 16.4.7, Operation Timing .

Execution Cycles of the DTC

Note 1. When transfer information read is skipped

Note 2. In full-address mode

Note 3. In short-address mode

Note 4. When neither SAR nor DAR is set to address-fixed

Note 5. When SAR or DAR is set to address-fixed

Note 6. When SAR and DAR are set to address-fixed

Note 7. When the block size is 2 or more. If the block size is 1, the cycle number for normal transfer is applied.

P: Block size (initial settings of CRAH and CRAL)

Cv: Cycles for access to vector transfer information storage destination

Ci: Cycles for access to transfer information storage destination address

Cr: Cycles for access to data read destination

Cw: Cycles for access to data write destination

(The unit is system clocks (ICLK) for "+ 1" in the Vector Read, Transfer Information Read, and Data Transfer Read columns and

"2" in the Internal Operation column.)

(Cv, Ci, Cr, and Cw vary depending on the corresponding access destination. For the number of cycles for respective access

destinations, refer to section 30, RAM, section 31, Flash Memory (FLASH), and section 5, I/O Registers.)

The DTC does not release the bus mastership during transfer information read and transfer information write. While

transfer information is not read or written, bus arbitration is made according to the priority determined by the bus master

For bus arbitration, refer to section 15, Buses .

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

Transfer Information Read

Transfer Information

16. Data Transfer Controller (DTCb)

Data Transfer

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