Pll Circuit; Internal Clock; System Clock; Peripheral Module Clock - Renesas RX100 Series User Manual

RX13T Group
9.5

PLL Circuit

The PLL circuit has a function to multiply the frequency from the oscillator.
9.6

Internal Clock

Clock sources of internal clock signals are the main clock, HOCO clock, LOCO clock, PLL clock, and dedicated
low-speed clock for the IWDT. The internal clocks listed below are produced from these sources.
(1) Operating clock of the CPU, DTC, ROM, and RAM: System clock (ICLK)
(2) Operating clock of peripheral modules: Peripheral module clock (PCLKB, and PCLKD)
(3) Operating clock of the FlashIF: FlashIF clock (FCLK)
(4) Operating clock for the CAC: CAC clock (CACCLK)
(5) Operating clock for the IWDT: IWDT-dedicated low-speed clock (IWDTCLK)
Frequencies of the internal clocks are set by the combinations of the division ratios selected by the FCK[3:0], ICK[3:0],
PCKB[3:0], and PCKD[3:0] bits in the SCKCR register, the clock source selected by the SCKCR3.CKSEL[2:0] bits, the
multiplier and divisor for the frequency of the PLL circuit set by the STC[5:0] and PLIDIV[1:0] bits in the PLLCR
register. If the value of any of these bits is changed, subsequent operation will be at the frequency determined by the new
value.
9.6.1

System Clock

The system clock (ICLK) is used as the operating clock of the CPU, DTC, ROM, and RAM.
The ICLK frequency is set by using the SCKCR.ICK[3:0] bits, the SCKCR3.CKSEL[2:0] bits, the STC[5:0] and
PLIDIV[1:0] bits in the PLLCR register.
9.6.2

Peripheral Module Clock

The peripheral module clocks (PCLKB, and PCLKD) are the operating clocks for use by peripheral modules.
The frequencies of the PCLKB, and PCLKD are set by using the PCKB[3:0] and PCKD[3:0] bits in the SCKCR register,
the SCKCR3.CKSEL[2:0] bits, the STC[5:0] and PLIDIV[1:0] bits in the PLLCR register.
The peripheral module clock used as the operating clock is PCLKD for S12AD, and PCLKB is for other modules.
9.6.3

FlashIF Clock

The FlashIF clock (FCLK) is used as the operating clock of the FlashIF.
The FCLK frequency is set by using the SCKCR.FCK[3:0] bits, the SCKCR3.CKSEL[2:0] bits, and the STC[5:0] and
PLIDIV[1:0] bits in the PLLCR register.
9.6.4

CAC Clock

The CAC clock (CACCLK) is an operating clock for the CAC module.
The CACCLK clocks include CACMCLK which is generated by the main clock oscillator, CACHCLK which is generated by
the high-speed on-chip oscillator, CACLCLK which is generated by the low-speed on-chip oscillator, and CACILCLK which
is generated by the IWDT-dedicated on-chip oscillator.
9.6.5

IWDT-Dedicated Clock

The IWDT-dedicated clock (IWDTCLK) is the operating clock for the IWDT.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
9. Clock Generation Circuit
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