Renesas RX100 Series User Manual page 769

RX13T Group
S 1 2
SCL0
SDA0
b7 b6
7-bit slave address
BBSY
MST
TRS
TDRE
TEND
RDRF
AASy
XXXX (Initial value/last data for transmission)
ICDRT
ICDRS
XXXX (Initial value/last data for reception)
ICDRR
ACKBT
ACKBR
START
NACKF
Figure 24.16 Slave Transmit Operation Timing (1) (7-Bit Address Format)
7 8 9 1
SCL0
SDA0
ACK
b1 b0 b7
DATA n-2
BBSY
MST
TRS
Transmit data (DATA n-1)
TDRE
TEND
RDRF
AASy
ICDRT DATA n-1
DATA n-2
ICDRS
ICDRR
ACKBT
ACKBR
STOP
NACKF
Write data to ICDRT register
(last data for transmission
[DATA n])
Figure 24.17 Slave Transmit Operation Timing (2)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Slave receive mode
3 4 5 6 7 8
b5 b4 b3 b2 b1 b0
R
7-bit address + R
X (ACK/NACK)
2 3 4 5 6
b6 b5 b4 b3 b2 b1
DATA n-1
DATA n-1
XXXX (Initial value/last data for reception)
0 (ACK)
[4]
Slave transmit mode
9 1 2 3 4
ACK
b7 b6 b5 b4
DATA 1
Transmit data (DATA 1)
DATA 1
DATA 1
0 (ACK)
0 (ACK)
Write data to Write data to
ICDRT register ICDRT register
(DATA 1) (DATA 2)
[3] [3]
7 8 9 1 2 3
ACK
b0 b7 b6 b5
DATA n
Transmit data (DATA n)
DATA n
0 (ACK)
0 (ACK)
2
24. I C-bus Interface (RIICa)
Automatic low hold (to prevent wrong transmission)
5 6 7 8 9
ACK
b3 b2 b1 b0 b7
Transmit data (DATA 2)
DATA 2
Write data to
ICDRT register
(DATA 3)
4 5 6 7 8 9
b4 b3 b2 b1 b0 NACK
DATA n
Dummy read
ICDRR register
(SCL0 line is released)
[5]
1 2 3 4
b6 b5 b4
DATA 2
DATA 3
DATA 2
0 (ACK)
[3]
P
1 (NACK)
Clear
Clear
STOP
NACKF flag
flag
[7]
Page 769 of 1041