Renesas RX100 Series User Manual page 567

RX13T Group
TOPS[1:0] Bits (Timeout Period Select)
These bits select the timeout period (period until the counter underflows) from among 128, 512, 1024, or 2048 cycles,
taking the divided clock specified by the CKS[3:0] bits as one cycle.
After the counter is refreshed, the combination of the CKS[3:0] and TOPS[1:0] bits determines the time (number of
IWDTCLK cycles) until the counter underflows.
Relations between the CKS[3:0] and TOPS[1:0] bit setting, the timeout period, and the number of IWDTCLK cycles are
listed in Table 22.2 .
Table 22.2 Settings and Timeout Periods
CKS[3:0] Bits
b7 b6 b5 b4
0 0 0 0
0 0 1 0
0 0 1 1
0 1 0 0
1 1 1 1
0 1 0 1
CKS[3:0] Bits (Clock Divide Ratio Select)
These bits select the IWDTCLK clock divide ratio from among divide-by 1, 16, 32, 64, 128, and 256. Combination with
the TOPS[1:0] bit setting, a count period between 128 and 524288 cycles of the IWDTCLK clock can be selected for the
IWDT.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
TOPS[1:0] Bits
b1 b0 Clock Divide Ratio
0 0 No division
0 1
1 0
1 1
0 0 Divide-by-16
0 1
1 0
1 1
0 0 Divide-by-32
0 1
1 0
1 1
0 0 Divide-by-64
0 1
1 0
1 1
0 0 Divide-by-128
0 1
1 0
1 1
0 0 Divide-by-256
0 1
1 0
1 1
22. Independent Watchdog Timer (IWDTa)
Timeout Period
(Number of Cycles) Cycles of IWDTCLK
128
512
1024
2048
128
512
1024
2048
128
512
1024
2048
128
512
1024
2048
128
512
1024
2048
128
512
1024
2048
128
512
1024
2048
2048
8192
16384
32768
4096
16384
32768
65536
8192
32768
65536
131072
16384
65536
131072
262144
32768
131072
262144
524288
Page 567 of 1041