Renesas RX100 Series User Manual page 401

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(3) Cascaded Operation Example (b)

Figure 19.22 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the I2AE bit in

TICCR has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the

MTU1.TIOR.IOA[3:0] bits have selected the MTIOC1A rising edge for the input capture timing while the

MTU2.TIOR.IOA[3:0] bits have selected the MTIOC2A rising edge for the input capture timing.

Under these conditions, the rising edge of both MTIOC1A and MTIOC2A is used for the MTU1.TGRA input capture

condition. For the MTU2.TGRA input capture condition, the MTIOC2A rising edge is used.

MTU2.TCNT value

Figure 19.22

Cascaded Operation Example (b)

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

As TICCR.I1AE = 0, data is not captured in MTU2.TGRA at

the MTIOC1A input timing.

19. Multi-Function Timer Pulse Unit 3 (MTU3c)

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