Timer Interrupt Enable Register (Tier) - Renesas RX100 Series User Manual

RX13T Group
19.2.8

Timer Interrupt Enable Register (TIER)

 MTU1.TIER, MTU2.TIER
Address(es): MTU1.TIER 0009 5384h, MTU2.TIER 0009 5404h
b7 b6
TTGE —
0 0
Value after reset:
 MTU0.TIER, MTU3.TIER
Address(es): MTU0.TIER 0009 5304h, MTU3.TIER 0009 5208h
b7 b6
TTGE —
Value after reset: 0 0
 MTU4.TIER
Address(es): MTU4.TIER 0009 5209h
b7 b6
TTGE TTGE2
0 0
Value after reset:
Bit Symbol Bit Name
b0 TGIEA TGR Interrupt Enable A
b1 TGIEB TGR Interrupt Enable B
b2 TGIEC TGR Interrupt Enable C
b3 TGIED TGR Interrupt Enable D
b4 TCIEV Overflow Interrupt Enable
b5 TCIEU Underflow Interrupt Enable
b6 TTGE2 A/D Converter Start Request Enable 2
b7 TTGE A/D Converter Start Request Enable
n = 4
The TIER register enables or disables interrupt requests from each channel. The MTU has a total of seven TIER
registers, two for MTU0 and one each for MTU1 to MTU5.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
TCIEU TCIEV — —
0 0 0 0
b5 b4 b3 b2
— TCIEV TGIED TGIEC TGIEB TGIEA
0 0 0 0
b5 b4 b3 b2
— TCIEV TGIED TGIEC TGIEB TGIEA
0 0 0 0
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
TGIEB TGIEA
0 0
b1 b0
0 0
b1 b0
0 0
Description
0: Interrupt requests (TGIA) disabled
1: Interrupt requests (TGIA) enabled
0: Interrupt requests (TGIB) disabled
1: Interrupt requests (TGIB) enabled
0: Interrupt requests (TGIC) disabled
1: Interrupt requests (TGIC) enabled
0: Interrupt requests (TGID) disabled
1: Interrupt requests (TGID) enabled
0: Interrupt requests (TCIV) disabled
1: Interrupt requests (TCIV) enabled
0: Interrupt requests (TCIU) disabled
1: Interrupt requests (TCIU) enabled
0: A/D converter start request generation by MTUn.TCNT
underflow (trough) disabled
1: A/D converter start request generation by MTUn.TCNT
underflow (trough) enabled
0: A/D converter start request generation disabled
1: A/D converter start request generation enabled
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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