C-Bus Control Register 2 (Iccr2) - Renesas RX100 Series User Manual

RX13T Group
2
24.2.2 I

C-bus Control Register 2 (ICCR2)

Address(es): RIIC0.ICCR2 0008 8301h
b7 b6
BBSY MST
0 0
Value after reset:
Bit Symbol Bit Name
b0 — Reserved
b1 ST Start Condition Issuance
Request
b2 RS Restart Condition Issuance
Request
b3 SP Stop Condition Issuance
Request
b4 — Reserved
b5 TRS Transmit/Receive Mode
b6 MST Master/Slave Mode
b7 BBSY Bus Busy Detection Flag
Note 1. When the ICMR1.MTWP bit is set to 1, bits MST and TRS can be written to.
ST Bit (Start Condition Issuance Request)
This bit is used to request transition to master mode and issuance of a start condition.
When this bit is set to 1 to request to issue a start condition, a start condition is issued when the BBSY flag is set to 0 (bus
free state).
For details on the start condition issuance, refer to section 24.10, Start Condition/Restart Condition/Stop Condition
Issuing Function .
[Setting condition]
 When 1 is written to the ST bit
[Clearing conditions]
 When 0 is written to the ST bit
 When a start condition has been issued (a start condition is detected)
 When the ICSR2.AL (arbitration-lost) flag is set to 1
 When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
Note: Set the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state).
Note that arbitration may be lost due to a start condition issuance error if the ST bit is set to 1 (start condition
issuance request) when the BBSY flag is set to 1 (bus busy state).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
TRS — SP RS
0 0 0 0
Description
This bit is read as 0. The write value should be 0.
0: Does not request to issue a start condition.
1: Requests to issue a start condition.
0: Does not request to issue a restart condition.
1: Requests to issue a restart condition.
0: Does not request to issue a stop condition.
1: Requests to issue a stop condition.
This bit is read as 0. The write value should be 0.
0: Receive mode
1: Transmit mode
0: Slave mode
1: Master mode
0: The I
1: The I
b1 b0
ST —
0 0
2
C-bus is released (bus free state).
2
C-bus is occupied (bus busy state).
2
24. I C-bus Interface (RIICa)
R/W
R/W
R/W
R/W
R/W
R/W
R/W*
R/W*
R
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