Modulation Duty Register (Mddr) - Renesas RX100 Series User Manual

RX13T Group
23.2.12

Modulation Duty Register (MDDR)

Address(es): SCI1.MDDR 0008 A032h, SCI5.MDDR 0008 A0B2h, SCI12.MDDR 0008 B312h
b7 b6
Value after reset: 1 1
The MDDR register corrects the bit rate adjusted by the BRR register.
When the SEMR.BRME bit is set to 1, the bit rate generated by the on-chip baud rate generator is evenly corrected
according to the settings of the MDDR register (M/256). The relationship between the MDDR register setting (M) and
the bit rate (B) is given in Table 23.24 .
The range of the value that can be set in the MDDR register is from 80h to FFh. A value other than these cannot be set.
The MDDR register is writable only when the TE and RE bits in the SCR register are 0.
Table 23.24 Relationship between MDDR Setting (M) and Bit Rate (B) When Bit Rate Modulation Function is
Used
SEMR Settings
Mode BGDM Bit ABCS Bit
Asynchronous, 0
multi-processor
communication
1
0
1
Clock synchronous, simple SPI*
Smart card interface
2 2
Simple I C*
B: Bit rate (bps)
M: MDDR setting (128 ≤ MDDR ≤ 256)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
PCLK: Operating frequency (MHz)
n and S: Determined by the settings of the SMR and SCMR registers as listed in Table 23.12 and Table 23.13, section
23.2.11, Bit Rate Register (BRR).
Note 1. Do not use this function in clock synchronous mode and in the highest speed settings in simple SPI mode (SMR.CKS[1:0] =
00b, SCR.CKE[1] = 0, and BRR = 0).
Note 2. Adjust the bit rate so that the widths at high and low level of the SCL output in simple I
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
1 1 1 1
BRR Setting
0

PCLK 10
N = ------------------------------------------------------ - 1
2n 1 –
 
64 2
0

PCLK 10
N = ------------------------------------------------------ - 1
2n 1 –
 
32 2
1
1

PCLK 10
N ------------------------------------------------------ - 1
=
2n 1 –
 
16 2
1

PCLK 10
N = --------------------------------------------------- - 1
256
2n 1 –
 
--------- -
8 2

PCLK
N ---------------------------------------------------- - 1
=
2n + 1
 
S 2

PCLK 10
N = ------------------------------------------------------ - 1
2n 1 –
 
64 2
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
1 1
Error (%)
6

–

256
Error = -------------------------------------------------------------------------------- 1


--------- -
B

M
B

6

–

256
Error = -------------------------------------------------------------------------------- 1


--------- -
B

M
B

6

–

256
Error =  -------------------------------------------------------------------------------- 1

--------- - B

M
B

6
–

B
M
6

10
–

256
Error = ----------------------------------------------------------------------------- - 1


--------- - B

M
B

6
–
256

--------- -
B
M
6

PCLK 10
–
256
2n 1 –
     
--------- -
64 2 N + 1
M
6

PCLK 10
–
256
2n 1 –
   --------- -   
32 2 N + 1
M
6

PCLK 10
–
256
2n 1 –
     
--------- -
16 2 N + 1
M
6

PCLK 10
–
256
2n + 1
     
--------- -
S 2 N + 1
M
2 2
C mode satisfy the I C-bus standard.
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