External Clock Input In Clock Synchronous Mode And Simple Spi Mode - Renesas RX100 Series User Manual

RX13T Group
Data reception
RXI interrupt
Read receive data in RDR
SCR.RE = 0
Make transition to software standby mode
Cancel software standby mode
Change operating mode?
Initialization
Start data reception
Figure 23.79 Example of Flowchart for Transition to Software Standby Mode during Reception
23.13.10

External Clock Input in Clock Synchronous Mode and Simple SPI Mode

In clock synchronous mode and simple SPI mode, the external clock SCKn must be input as follows:
High-pulse period, low-pulse period = 2 PCLK cycles or more, period = 6 PCLK cycles or more
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Yes
Yes
23. Serial Communications Interface (SCIg, SCIh)
[ 1 ] Data being received is invalid.
No
[ 1 ]
[ 2 ] Setting for the module stop state is included.
[ 2 ]
No
SCR.RE = 1
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