Renesas RX100 Series User Manual page 264

RX13T Group
Match and
RRS bit = 1
Compare vector
numbers. Match?
Read DTC vector
Read transfer information
CHNE bit = 1?
No
Yes
MD[1:0] bits = 01b?
(Repeat transfer mode?)
No
WBDIS = 0 and
Last data transfer?
(Transfer counter = 1?)
DISEL bit = 1?
No
Clear interrupt status flag
Transfer data
Write back
transfer information
Figure 16.5 Operation Flowchart of the DTC
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Start
Unmatch or RRS bit = 0
Next transfer
Yes
Yes
*1
No
Yes
Transfer data
Write back
*2
transfer information
ICU.DTCERn.DTCE
bit is cleared
An interrupt to the
CPU is generated
Note 1. Counter value before starting data transfer
End
Note 2. Write-back is skipped when the WBDIS bit is 1.
Note 3. The DTCE bit is not cleared when the WBDIS bit is 1.
CHNS bit = 0?
No
WBDIS = 0 and
Last data transfer?
(Transfer counter = 1?)
No
Transfer data
Write back
*2
transfer information
*3
An interrupt to the
CPU is generated
16. Data Transfer Controller (DTCb)
Yes
Yes
*1
Transfer data
Write back
*2 *2
transfer information
Update start address
of transfer information
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