Request Sources; Allocating Transfer Information And Dtc Vector Table - Renesas RX100 Series User Manual

RX13T Group
16.3

Request Sources

The DTC data transfer is triggered by an interrupt request. Setting the ICU.DTCERn.DTCE bit (n = interrupt vector
number) to 1 selects the corresponding interrupt request as a request source for the DTC.
For the correspondence between the DTC request sources and the vector addresses, refer to section 14.3.1, Interrupt
Vector Table in section 14, Interrupt Controller (ICUb) . For request by software, refer to section 14.2.5, Software
Interrupt Generation Register (SWINTR) in section 14, Interrupt Controller (ICUb) .
Once the DTC has accepted a transfer request, it does not accept another transfer request until transfer for that single
request is completed, regardless of the priority of the requests.
When multiple transfer requests are generated during data transfer by the DTC, the request with the highest priority on
completion of the current transfer is accepted. When multiple transfer requests are generated while the DTCST.DTCST
bit is 0 (DTC module stop), the request with the highest priority at the moment when the bit is subsequently set to 1
(DTC module start) is accepted.
The DTC performs the following operations at the start of a single data transfer (or the last of the consecutive transfers in
the case of a chain transfer).
 On completion of a specified number of data transfer, the ICU.DTCERn.DTCE bit is set to 0 and an interrupt is
requested to the CPU.
 If the MRB.DISEL bit is 1, an interrupt is requested to the CPU on completion of data transfer.
 For the other transfers, the interrupt status flag of the request source is set to 0 at the start of data transfer.
16.3.1

Allocating Transfer Information and DTC Vector Table

The DTC reads the start address of the transfer information corresponding to each request source from the vector table
and reads the transfer information starting at that address.
The vector table should be located so that the lower 10 bits of the base address (start address) are 0. Use the DTC vector
base register (DTCVBR) to set the base address of the DTC vector table.
Transfer information is allocated in the RAM area. Transfer information can be allocated in the ROM area when the
MRA.WBDIS bit is set to 1. The start address of the transfer information n with vector number n should be allocated at
DTCVBR + 4n.
Transfer information should be aligned on a 4-byte boundary. The size of a transfer information is 12 bytes in short-
address mode or 16 bytes in full-address mode. Use the DTCADMOD.SHORT bit to select short-address mode (SHORT
bit = 1) or full-address mode (SHORT bit = 0).
Figure 16.3 shows the relationship between the DTC vector table and transfer information.
Figure 16.4 shows the allocation of transfer information in the RAM area. The lower addresses vary according to the
endian of the corresponding allocation area. For details, refer to section 16.9.2, Allocating Transfer Information .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
16. Data Transfer Controller (DTCb)
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