Block Transfer Mode - Renesas RX100 Series User Manual

RX13T Group
16.4.5

Block Transfer Mode

This mode allows single-block data transfer on a single transfer request.
Specify either transfer source or transfer destination for the block area by the MRB.DTS bit. The block size can be set to
1 to 256 bytes, 1 to 256 words, or 1 to 256 longwords.
When transfer of the specified one block is completed, the initial values of the block size counter CRAL and the address
register (the SAR register when the MRB.DTS bit is 1 or the DAR register when the DTS bit is 0) specified in the block
area are restored. The other address register is incremented or decremented continuously or remains unchanged.
The transfer count (block count) can be set to 1 to 65536. This mode enables an interrupt request to the CPU to be
generated at the end of specified-count block transfer.
Table 16.8 lists register functions in block transfer mode, and Figure 16.8 shows the memory map of block transfer
mode.
Table 16.8 Register Functions in Block Transfer Mode
Register Description
SAR Transfer source address
DAR Transfer destination address
CRAH Retains initial value of block size
CRAL Block size counter
CRB Block transfer counter
Note 1. Write-back operation is skipped when the MRA.WBDIS bit is 1.
Note 2. Write-back operation is skipped when address is fixed.
SAR
Figure 16.8 Memory Map of Block Transfer Mode (Transfer Destination: Block Area)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Value Written Back by Writing Transfer Information*
When MRB.DTS Bit is 0
Increment/decrement/fixed*
DAR register initial value
CRAH
CRAH
CRB – 1
Transfer source data area
First block
nth block
2
Transfer destination data area
(set to block area)
Transfer
Block area
16. Data Transfer Controller (DTCb)
1
When MRB.DTS Bit is 1
SAR register initial value
Increment/decrement/fixed*
DAR
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