Dtc Transfer Source Register (Sar); Dtc Transfer Destination Register (Dar) - Renesas RX100 Series User Manual

RX13T Group
16.2.4

DTC Transfer Source Register (SAR)

Address(es): (inaccessible directly from the CPU)
b31 b30
Value after reset: x x
b15 b14
Value after reset: x x
x: Undefined
SAR register is used to set the transfer source start address.
In full-address mode, 32 bits are valid.
In short-address mode, lower 24 bits are valid and upper 8 bits (b31 to b24) are ignored. The address of this register is
extended by the value specified by b23.
SAR register cannot be accessed directly from the CPU.
16.2.5

DTC Transfer Destination Register (DAR)

Address(es): (inaccessible directly from the CPU)
b31 b30
x x
Value after reset:
b15 b14
Value after reset: x x
x: Undefined
DAR register is used to set the transfer destination start address.
In full-address mode, 32 bits are valid.
In short-address mode, lower 24 bits are valid and upper 8 bits (b31 to b24) are ignored. The address of this register is
extended by the value specified by b23.
DAR register cannot be accessed directly from the CPU.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b29 b28 b27 b26
x x x x
b13 b12 b11 b10
x x x x
b29 b28 b27 b26
x x x x
b13 b12 b11 b10
x x x x
b25 b24 b23 b22
x x x x
b9 b8 b7 b6
x x x x
b25 b24 b23 b22
x x x x
b9 b8 b7 b6
x x x x
16. Data Transfer Controller (DTCb)
b21 b20 b19 b18
x x x x
b5 b4 b3 b2
x x x x
b21 b20 b19 b18
x x x x
b5 b4 b3 b2
x x x x
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b17 b16
x x
b1 b0
x x
b17 b16
x x
b1 b0
x x