Renesas RX100 Series User Manual page 873

RX13T Group
Table 26.13 Times for Conversion during Scanning (in Numbers of Cycles of ADCLK and PCLK)
Item
Scan start A/D conversion on
processing time group under group
1, 2
* * priority control.
A/D conversion
when self-diagnosis
is enabled
Other than above
Channel-dedicated Sampling time
sample-and-hold
1
processing time*
Wait time between sampling and A/D conversion
Disconnection detection assistance processing time
Self-diagnosis Sampling time
conversion
Time for conversion by successive approximation
1
processing time*
Normal A/D conversion is to be started after
completion of self-diagnosis conversion.
A/D conversion for self-diagnosis is to be started
after completion of conversion for continuous scan
on the last channel specified.
A/D conversion Sampling time
processing time* 1
Time for conversion by successive approximation
Channel-dedicated sample-and-hold end processing time
1
Scan end processing time*
Note 1. For t , t , t
D SPLSH DIAG
Note 2. This is the maximum time required from software writing or trigger input to A/D conversion start.
Note 3. The value is fixed to 0Fh (15 ADCLK) when the internal reference voltage is A/D-converted.
Software trigger
Synchronous trigger
ADST bit
A/D converter
Figure 26.26 Scan Conversion Timing (Activated by Software or Synchronous Trigger)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
The low-priority group is to
be stopped. (The priority
group is activated after
low-priority group B is
stopped due to an A/D
conversion source of the
priority group.)
The low-priority group is
not to be stopped.
(Activation by an A/D
conversion source of the
priority group.)
A/D conversion for self-
diagnosis is to be started.
, t , and t , see Figure 26.26 and Figure 26.27.
CONV ED
t
D
Waiting
Synchronous
Symbol Trigger (MTU)
t 3 PCLKB + 6 ADCLK
D
2 PCLKB + 4 ADCLK
2 PCLKB + 6 ADCLK
2 PCLKB + 4 ADCLK
t t The setting of ADSHCR.SSTSH[7:0] (initial value =
SPLSH SH
1Ah) × ADCLK
t 13 ADCLK
W
t The setting of ADNDIS[3:0] (initial value = 00h) ×
DIS
3
ADCLK*
t t The setting of ADSSTR0 (initial value = 0Dh) × ADCLK
DIAG SPL
t 32 ADCLK
SAM
t 2 ADCLK
DED
t 2 ADCLK
DSD
t t The setting of ADSSTRn (n = 0 to 7, O)
CONV SPL
(initial value = 0Dh) × ADCLK
t 32 ADCLK
SAM
t 3 ADCLK
SHED
t 1 PCLKB + 3 ADCLK
ED
t
SCAN
t t
SPLSH DIAG
Sampling DIAG conversion
26. 12-Bit A/D Converter (S12ADF)
Type/Conditions
Asynchronous Software
Trigger Trigger
— —
— —
4 PCLKB+ 6 ADCLK
6 ADCLK
2 PCLKB + 4 ADCLK
4 ADCLK
t t
CONV ED
End
A/D conversion
processing
Page 873 of 1041
Unit
Cycle