Timer A/D Converter Start Request Cycle Set Registers (Tadcora, Tadcorb); Timer A/D Converter Start Request Cycle Set Buffer Registers (Tadcobra, Tadcobrb) - Renesas RX100 Series User Manual

RX13T Group
19.2.35 Timer A/D Converter Start Request Cycle Set Registers (TADCORA,
TADCORB)
Address(es): MTU4.TADCORA 0009 5244h, MTU4.TADCORB 0009 5246h
b15 b14
Value after reset: 1 1
Note: TADCORA and TADCORB must not be accessed in 8 bits; it should be accessed in 16 bits.
Note 1. When the A/D converter start request delaying function linked with skipping function 1 (for details, refer to section 19.3.9 (5), A/
D Converter Start Request Delaying Function Linked with Interrupt Skipping Function 1) is used, the value of this register should
be 0002h to TCDRA setting – 2 in MTU4.
Note 2. When interrupt skipping function 2 is used and the difference between the TADCORA value and the TADCORB value is small,
the skipping count may not be counted correctly and the A/D converter start request may not be generated with the expected
timing in some cases. The TADCORA and TADCORB values should satisfy the following conditions.
(1) When skipping function 2 is specified with the skipping count set to 0
- The difference between the TADCORA and TADCORB values should be equal to or greater than 4.
- The TADCORA compare interval should be equal to or greater than 4 PCLKB cycles (the TADCORA update value should
be the previous value + 4 or greater, or previous value – 4 or smaller).
- The TADCORB compare interval should be equal to or greater than 4 PCLKB cycles (the TADCORB update value should
be the previous value + 4 or greater, or previous value – 4 or smaller).
(2) When skipping function 2 is specified with the skipping count set to 1 or greater
- The difference between the TADCORA and TADCORB values should be equal to or greater than 2.
- The TADCORB compare interval should be equal to or greater than 2 PCLKB cycles (the TADCORB update value should
be the previous value + 2 or greater, or previous value – 2 or smaller)
TADCORA and TADCORB are 16-bit readable/writable registers that issue a corresponding A/D converter start request
when the MTUn.TCNT (n = 4) count reaches the value in TADCORA or TADCORB.
MTUn.TADCORA and TADCORB are initialized to FFFFh by a reset.
19.2.36 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA,
TADCOBRB)
Address(es): MTU4.TADCOBRA 0009 5248h, MTU4.TADCOBRB 0009 524Ah
b15 b14
1 1
Value after reset:
Note: TADCOBRA and TADCOBRB must not be accessed in 8 bits; it should be accessed in 16 bits.
TADCOBRA and TADCOBRB are 16-bit readable/writable registers whose values are transferred to TADCORA and
TADCORB, respectively, when the crest or trough of the MTUn.TCNT count is reached.
TADCOBRA and TADCOBRB are initialized to FFFFh by a reset.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
1 1 1 1
b13 b12 b11 b10
1 1 1 1
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b9 b8 b7 b6
1 1 1 1
b9 b8 b7 b6
1 1 1 1
b5 b4 b3 b2
1 1 1 1
b5 b4 b3 b2
1 1 1 1
Page 380 of 1041
b1 b0
1 1
b1 b0
1 1