Master Transmit Operation - Renesas RX100 Series User Manual

RX13T Group
24.3.3

Master Transmit Operation

In master transmit operation, the RIIC outputs the SCL clock and transmitted data signals as the master device, and the
slave device returns acknowledgments. Figure 24.6 shows an example of usage of master transmission and Figure 24.7
to Figure 24.9 show the timing of operations in master transmission.
The following describes the procedure and operations for master transmission.
(1) Initial settings. For details, refer to section 24.3.2, Initial Settings .
(2) Read the ICCR2.BBSY flag to check that the bus is open, and then set the ICCR2.ST bit to 1 (start condition
issuance request). Upon receiving the request, the RIIC issues a start condition. At the same time, the BBSY flag
and the ICSR2.START flag are automatically set to 1 and the ST bit is automatically set to 0. At this time, if the start
condition is detected and the internal levels for the SDA output state and the levels on the SDA0 line have matched
while the ST bit is 1, the RIIC recognizes that issuing of the start condition as requested by the ST bit has been
successfully completed, and bits MST and TRS in the ICCR2 register are automatically set to 1, placing the RIIC in
master transmit mode. The ICSR2.TDRE flag is also automatically set to 1 in response to setting of the TRS bit to 1.
(3) Check that the ICSR2.TDRE flag is 1, and then write the value for transmission (the slave address and the R/W# bit)
to the ICDRT register. Once the data for transmission are written to the ICDRT register, the TDRE flag is
automatically set to 0, the data are transferred from the ICDRT register to the ICDRS register, and the TDRE flag is
again set to 1. After the byte containing the slave address and R/W# bit has been transmitted, the value of the TRS
bit is automatically updated to select master transmit or master receive mode in accord with the value of the
transmitted R/W# bit. If the value of the R/W# bit was 0, the RIIC continues in master transmit mode.
Because the ICSR2.NACKF flag being 1 at this time indicates that no slave device recognized the address or there
was an error in communications, write 1 to the ICCR2.SP bit to issue a stop condition.
For data transmission with an address in the 10-bit format, start by writing 1111 0b, the 2 higher-order bits of the
slave address, and W to the ICDRT register as the first address transmission. Then, as the second address
transmission, write the 8 lower-order bits of the slave address to the ICDRT register.
(4) After confirming that the ICSR2.TDRE flag is 1, write the data for transmission to the ICDRT register. The RIIC
automatically holds the SCL0 line low until the data for transmission are ready or a stop condition is issued.
(5) After all bytes of data for transmission have been written to the ICDRT register, wait until the value of the
ICSR2.TEND flag returns to 1, and then set the ICCR2.SP bit to 1 (stop condition issuance request). Upon receiving
a stop condition issuance request, the RIIC issues the stop condition.
(6) Upon detecting the stop condition, the RIIC automatically sets bits MST and TRS in the ICCR2 register to 00b and
enters slave receive mode. Furthermore, it automatically sets the TDRE and TEND flags to 0, and sets the
ICSR2.STOP flag to 1.
(7) After checking that the ICSR2.STOP flag is 1, set the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
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24. I C-bus Interface (RIICa)
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