Timer I/O Control Register (Tior) - Renesas RX100 Series User Manual

32-bit mcu
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19.2.6

Timer I/O Control Register (TIOR)

 MTU0.TIORH, MTU1.TIOR, MTU2.TIOR, MTU3.TIORH, MTU4.TIORH
Address(es): MTU0.TIORH 0009 5302h, MTU1.TIOR 0009 5382h, MTU2.TIOR 0009 5402h, MTU3.TIORH 0009 5204h,
MTU4.TIORH 0009 5206h
b7
b6
IOB[3:0]
0
0
Value after reset:
Bit
Symbol
b3 to b0
IOA[3:0]
b7 to b4
IOB[3:0]
Note 1. When the value of IOn[3:0] (n = A, B) is changed to the output-prohibited state (0000b or 0100b) during low, high, or toggle
output at compare match, this register is in Hi-Z.
 MTU0.TIORL, MTU3.TIORL, MTU4.TIORL
Address(es): MTU0.TIORL 0009 5303h, MTU3.TIORL 0009 5205h, MTU4.TIORL 0009 5207h
b7
b6
IOD[3:0]
0
0
Value after reset:
Bit
Symbol
Bit Name
b3 to b0
IOC[3:0]
I/O Control C*
b7 to b4
IOD[3:0]
I/O Control D*
Note 1. When the value of IOn[3:0] (n = C, D) is changed to the output-prohibited state (0000b or 0100b) during low, high, or toggle
output at compare match, this register is in Hi-Z.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5
b4
b3
b2
IOA[3:0]
0
0
0
0
Bit Name
1
I/O Control A*
1
I/O Control B*
b5
b4
b3
b2
IOC[3:0]
0
0
0
0
Description
1
Refer to the following tables.
MTU0.TIORL: Table 19.22
MTU3.TIORL: Table 19.26
MTU4.TIORL: Table 19.28
1
Refer to the following tables.
MTU0.TIORL: Table 19.14
MTU3.TIORL: Table 19.18
MTU4.TIORL: Table 19.20
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1
b0
0
0
Description
Refer to the following tables.
MTU0.TIORH: Table 19.21
MTU1.TIOR: Table 19.23
MTU2.TIOR: Table 19.24
MTU3.TIORH: Table 19.25
MTU4.TIORH: Table 19.27
Refer to the following tables.
MTU0.TIORH: Table 19.13
MTU1.TIOR: Table 19.15
MTU2.TIOR: Table 19.16
MTU3.TIORH: Table 19.17
MTU4.TIORH: Table 19.19
b1
b0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Page 337 of 1041

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