Oscillation Stop Detection Status Register (Ostdsr) - Renesas RX100 Series User Manual

RX13T Group
9.2.11

Oscillation Stop Detection Status Register (OSTDSR)

Address(es): 0008 0041h
b7 b6
— —
0 0
Value after reset:
Bit Symbol
b0 OSTDF
b7 to b1 —
Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
Note 1. This bit can only be set to 0.
OSTDF Flag (Oscillation Stop Detection Flag)
This bit is a flag to indicate the main clock status. When the OSTDF flag is 1, it indicates that the main clock oscillation
stop has been detected.
Once the main clock oscillation stop is detected, the OSTDF flag is not set to 0 even though the main clock oscillation is
restarted. The OSTDF flag is set to 0 by reading 1 from the bit and then writing 0. At least three ICLK cycles of wait time
is necessary between writing 0 to the OSTDF flag and reading the OSTDF flag as 0. If the OSTDF flag is set to 0 while
the main clock oscillation is stopped, the OSTDF flag becomes 0 and then returns to 1.
When the main clock oscillator (010b) or PLL (100b) is selected by the clock source select bits in system clock control
register 3 (SCKCR3.CKSEL[2:0]), the OSTDF flag cannot be modified to 0. The OSTDF flag should be set to 0 after
switching the clock source to a source other than the main clock oscillator and the PLL.
[Setting condition]
 The main clock oscillation is stopped with the OSTDCR.OSTDE bit being 1 (oscillation stop detection function
enabled).
[Clearing condition]
 1 is read and then 0 is written when the SCKCR3.CKSEL[2:0] bits are neither 010b nor 100b.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
Bit Name
Oscillation Stop Detection Flag
Reserved
b1 b0
— OSTDF
0 0
Description
0: The main clock oscillation stop has not been detected.
1: The main clock oscillation stop has been detected.
These bits are read as 0 and cannot be modified.
9. Clock Generation Circuit
R/W
R/(W)
1
*
R
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