Renesas RX100 Series User Manual page 33

RX13T Group
Table 1.1 Outline of Specifications (2/3)
Classification Module/Function
Interrupt Interrupt controller (ICUb)
DMA Data transfer controller
(DTCb)
I/O ports General I/O ports
Multi-function pin controller (MPC)
Timers Multi-function timer pulse
unit 3 (MTU3c)
Port output enable 3
(POE3C)
Compare match timer
(CMT)
Independent watchdog
timer (IWDTa)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Description
 Interrupt vectors: 256
 External interrupts: 7 (NMI, IRQ0 to IRQ5 pins)
 Non-maskable interrupts: 5 (NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)
 16 levels specifiable for the order of priority
 Transfer modes: Normal transfer, repeat transfer, and block transfer
 Activation sources: External interrupts and interrupt requests from peripheral functions
 Sequence transfer
48-/32-pin
 I/O: 38/22
 Input: 1/1
 Pull-up resistors: 38/22
 Open-drain outputs: 30/18
 5-V tolerance: 2/2
Capable of selecting the input/output function from multiple pins
 6 units (16 bis × 6 channels)
 Provides up to 16 pulse-input/output lines and three pulse-input lines
 Select from among fourteen counter-input clock signals for each channel (PCLK/1, PCLK/2, PCLK/4,
PCLK/8, PCLK/16, PCLK/32, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC,
MTCLKD, MTIOC1A) other than channel 1/3/4, for which only eleven signals are available, channel 2
for 12, channel 5 for 10
 26 output compare/input capture registers
 Counter clear operation (with compare match- or input capture-sourced simultaneous counter clear
capability)
 Simultaneous writing to multiple timer counters (TCNT)
 Simultaneous register input/output by synchronous counter operation
 Buffer operation
 Cascaded operation
 28 interrupt sources
 Automatic transfer of register data
 Pulse output modes: Toggle/PWM/complementary PWM/reset-synchronized PWM
 Complementary PWM output mode
3-phase non-overlapping waveform output for inverter control
Automatic dead time setting
Adjustable PWM duty cycle: from 0 to 100%
A/D conversion request delaying function
Interrupt at crest/trough can be skipped
Double buffer function
 Reset-synchronized PWM mode
Outputs three phases each for positive and negative PWM waveforms in user-specified duty cycle
 Phase counting modes: 16-bit mode (channel 1 and 2)/32-bit mode (channel 1 and 2)
 Dead time compensation counter function
 A/D converter start trigger can be generated
 A/D converter start triggers can be skipped
 Signals from the input capture and external counter clock pins are input via a digital filter
Controls the high-impedance state of the MTU's waveform output pins
 (16 bits × 2 channels) × 1 units
 Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
 14 bits × 1 channel
 Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
1. Overview
Page 33 of 1041