Deep Sleep Mode; Entry To Deep Sleep Mode - Renesas RX100 Series User Manual

RX13T Group
11.6.2

Deep Sleep Mode

11.6.2.1

Entry to Deep Sleep Mode

When a WAIT instruction is executed with the MSTPCRC.DSLPE bit set to 1, the MSTPCRA.MSTPA28 bit set to 1,
and the SBYCR.SSBY bit cleared to 0, a transition to deep sleep mode is made. *
In deep sleep mode, the CPU and the DTC, ROM, and RAM clocks stop. Peripheral functions do not stop.
Counting by the IWDT stops if a transition to deep sleep mode is made while the IWDT is being used in auto-start mode
and the OFS0.IWDTSLCSTP bit is 1. In the same way, counting by the IWDT stops if a transition to deep sleep mode is
made while the IWDT is being used in register start mode and the IWDTCSTPR.SLCSTP bit is 1.
Furthermore, counting by the IWDT continues if a transition to deep sleep mode is made while the IWDT is being used
in auto-start mode and the OFS0.IWDTSLCSTP bit is 0 (counting by the IWDT continues through transitions to low
power consumption modes). In the same way, counting by the IWDT continues if a transition to deep sleep mode is made
while the IWDT is being used in register start mode and the IWDTCSTPR.SLCSTP bit is 0.
To use deep sleep mode, make the following settings and then execute a WAIT instruction.
2
(1) Set the PSW.I bit *
of the CPU to 0.
(2) Set the interrupt request destination *
4
(3) Set the priority * of the interrupt to be used for exit from deep sleep mode to a level higher than the setting of the
2
PSW.IPL[3:0] bits *
(4) Set the IERm.IENj bit *
(5) Read the I/O register that is written last and confirm that the written value has been reflected.
(6) Execute a WAIT instruction (executing a WAIT instruction causes automatic setting of the PSW.I bit *
to 1).
Note 1. Transition to deep sleep mode might not be possible, depending on the operating state of the DTC.
Before setting the MSTPCRA.MSTPA28 bit to 1, set the DTCST.DTCST bit of the DTC to 0 to avoid activating
the DTC.
Note 2. For details, refer to section 2, CPU.
Note 3. For details, refer to section 14.4.3, Selecting Interrupt Request Destinations.
Note 4. For details, refer to section 14, Interrupt Controller (ICUb).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
3
to be used for exit from deep sleep mode.
of the CPU.
4
to 1 for the interrupt.
11. Low Power Consumption
1
2
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of the CPU