Usage Notes; Start Address Of Transfer Information; Allocating Transfer Information - Renesas RX100 Series User Manual

RX13T Group
16.9

Usage Notes

16.9.1

Start Address of Transfer Information

Set multiples of 4 for the start addresses of the transfer information to be specified in the DTC vector table. If any value
other than a multiple of 4 is specified, access still proceeds with the lower 2 bits of the address regarded as 00b.
16.9.2

Allocating Transfer Information

Allocate transfer information in the memory area according to the endian of the area as shown in Figure 16.26 .
For example, when writing CRA and CRB settings in 16-bit units in big endian, write the CRA setting to the address plus
8h (Ch) and the CRB setting to the address plus Ah (Eh). In little endian, write the CRB setting to the address plus 8h
(Ch) and the CRA setting to the address plus Ah (Eh). When writing CRA and CRB settings in 32-bit units, allocate the
CRA setting at the MSB side of the 32 bits and the CRB setting at the LSB side, and write the settings to the address plus
8h (Ch), regardless of endian.
Allocation of transfer information to
Address
4n
4(n+1)
4(n+2)
Allocation of transfer information to
Address
4n
4(n+1)
4(n+2)
4(n+3)
Figure 16.26 Allocation of Transfer Information
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
little-endian area
(Short-address mode)
Lower address
3 2 1 0
MRA SAR
MRB DAR
CRA CRB
4 bytes
little-endian area
(Full-address mode)
Lower address
3 2 1 0
Rsvd.
MRA MRB MRC
(00h)
SAR
DAR
CRA CRB
4 bytes
16. Data Transfer Controller (DTCb)
Allocation of transfer information to
big-endian area
(Short-address mode)
Lower address
Address 0 1
4n MRA
4(n+1) MRB
4(n+2)
CRA
4 bytes
Allocation of transfer information to
big-endian area
(Full-address mode)
Lower address
Address 0 1
4n MRA MRB
4(n+1) SAR
4(n+2) DAR
4(n+3) CRA
4 bytes
2 3
SAR
DAR
CRB
2 3
Rsvd.
MRC
(00h)
CRB
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