Non-Maskable Interrupt Enable Register (Nmier) - Renesas RX100 Series User Manual

RX13T Group
14.2.11

Non-Maskable Interrupt Enable Register (NMIER)

Address(es): ICU.NMIER 0008 7581h
b7 b6
— —
Value after reset: 0 0
Bit Symbol
b0 NMIEN
b1 OSTEN
b2 —
b3 IWDTEN
b4 LVD1EN
b5 LVD2EN
b7, b6 —
Note 1. A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
NMIEN Bit (NMI Pin Interrupt Enable)
This bit enables the NMI pin interrupt.
A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
Writing 0 to this bit is disabled.
OSTEN Bit (Oscillation Stop Detection Interrupt Enable)
This bit enables the oscillation stop detection interrupt.
A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
Writing 0 to this bit is disabled.
IWDTEN Bit (IWDT Underflow/Refresh Error Enable)
This bit enables the IWDT underflow/refresh error interrupt.
A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
Writing 0 to this bit is disabled.
LVD1EN Bit (Voltage Monitoring 1 Interrupt Enable)
This bit enables the voltage monitoring 1 interrupt.
A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
Writing 0 to this bit is disabled.
LVD2EN Bit (Voltage Monitoring 2 Interrupt Enable)
This bit enables the voltage monitoring 2 interrupt.
A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
Writing 0 to this bit is disabled.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
LVD2E LVD1E IWDTE
—
N N N
0 0 0 0
Bit Name
NMI Pin Interrupt Enable
Oscillation Stop Detection Interrupt
Enable
Reserved
IWDT Underflow/Refresh Error
Enable
Voltage Monitoring 1 Interrupt
Enable
Voltage Monitoring 2 Interrupt
Enable
Reserved
b1 b0
OSTEN NMIEN
0 0
Description
0: NMI pin interrupt is disabled
1: NMI pin interrupt is enabled
0: Oscillation stop detection interrupt is disabled
1: Oscillation stop detection interrupt is enabled
This bit is read as 0. The write value should be 0.
0: IWDT underflow/refresh error interrupt is disabled
1: IWDT underflow/refresh error interrupt is enabled
0: Voltage monitoring 1 interrupt is disabled
1: Voltage monitoring 1 interrupt is enabled
0: Voltage monitoring 2 interrupt is disabled
1: Voltage monitoring 2 interrupt is enabled
These bits are read as 0. The write value should be 0.
14. Interrupt Controller (ICUb)
R/W
R/(W)
* 1
R/(W)
1
*
R/W
R/(W)
1
*
R/(W)
1
*
R/(W)
* 1
R/W
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