Iwdt Control Register (Iwdtcr) - Renesas RX100 Series User Manual

RX13T Group
22.2.2

IWDT Control Register (IWDTCR)

Address(es): IWDT.IWDTCR 0008 8032h
b15 b14
— —
Value after reset: 0 0
Bit Symbol
b1, b0 TOPS[1:0]
b3, b2 —
b7 to b4 CKS[3:0]
b9, b8 RPES[1:0]
b11, b10 —
b13, b12 RPSS[1:0]
b15, b14 —
There are some restrictions on writing to the IWDTCR register. For details, refer to section 22.3.2, Control over
Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers .
In auto-start mode, the settings in the IWDTCR register are disabled, and the settings in option function select register 0
(OFS0) are enabled. The bit setting made to the IWDTCR register can also be made in the OFS0 register. For details,
refer to section 22.3.8, Correspondence between Option Function Select Register 0 (OFS0) and IWDT
Registers .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
RPSS[1:0] — —
1 1 0 0
Bit Name
Timeout Period Select
Reserved
Clock Divide Ratio Select
Window End Position Select
Reserved
Window Start Position Select
Reserved
22. Independent Watchdog Timer (IWDTa)
b9 b8 b7 b6
RPES[1:0] CKS[3:0]
1 1 1 1
Description
b1 b0
0 0: 128 cycles (007Fh)
0 1: 512 cycles (01FFh)
1 0: 1024 cycles (03FFh)
1 1: 2048 cycles (07FFh)
These bits are read as 0. Writing to these bits has no effect.
b7 b4
0 0 0 0: No division
0 0 1 0: Divide-by-16
0 0 1 1: Divide-by-32
0 1 0 0: Divide-by-64
1 1 1 1: Divide-by-128
0 1 0 1: Divide-by-256
Other settings are prohibited.
b9 b8
0 0: 75%
0 1: 50%
1 0: 25%
1 1: 0% (window end position is not specified.)
These bits are read as 0. Writing to these bits has no effect.
b13 b12
0 0: 25%
0 1: 50%
1 0: 75%
1 1: 100% (window start position is not specified.)
These bits are read as 0. Writing to these bits has no effect.
b5 b4 b3 b2
— —
1 1 0 0
Page 566 of 1041
b1 b0
TOPS[1:0]
1 1
R/W
R/W
R
R/W
R/W
R
R/W
R