Control Over Writing To The Iwdtcr, Iwdtrcr, And Iwdtcstpr Registers - Renesas RX100 Series User Manual

RX13T Group
22.3.2

Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers

Writing to the IWDTCR, IWDTRCR, or IWDTCSTPR register is only possible once between the release from the reset
state and the first refresh operation.
After a refresh operation (counting starts) or the IWDTCR, IWDTRCR, or IWDTCSTPR register is written to, the
protection signal in the IWDT becomes 1 to protect registers IWDTCR, IWDTRCR, and IWDTCSTPR against
subsequent attempts at writing.
This protection is released by the reset source of the IWDT. With other reset sources, the protection is not released.
Figure 22.5 shows control waveforms produced in response to writing to the IWDTCR register.
RES# pin
Peripheral module clock
(PCLK)
Data written to IWDTCR
register
IWDTCR register write
signal (internal signal)
IWDTCR register
Register
protection signal
(internal signal)
Figure 22.5 Control Waveforms Produced in Response to Writing to the IWDTCR Register
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
00F3h
Writing disabled
33F3h (initial value)
IWDTCR register is protected
(writing-disabled period)
Writing is possible
22. Independent Watchdog Timer (IWDTa)
3300h
00F3h 00F3h 33F3h (initial value)
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