Serial Extended Mode Register (Semr) - Renesas RX100 Series User Manual

RX13T Group
Smaller settings of the SMR.CKS[1:0] bits and larger settings of the BRR register reduce difference in the length of the
1-bit period.
23.2.13

Serial Extended Mode Register (SEMR)

Address(es): SCI1.SEMR 0008 A027h, SCI5.SEMR 0008 A0A7h, SCI12.SEMR 0008 B307h
b7 b6
RXDES
BGDM NFEN
EL
0 0
Value after reset:
Bit Symbol Bit Name
b0 ACS0 Asynchronous Mode
Clock Source Select
b1 — Reserved
b2 BRME Bit Rate Modulation
Enable
b3 — Reserved
b4 ABCS Asynchronous Mode
Base Clock Select
b5 NFEN Digital Noise Filter
Function Enable
b6 BGDM Baud Rate Generator
Double-Speed Mode
Select
b7 RXDESEL Asynchronous Start Bit
Edge Detection Select
Note 1. Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
The SEMR register is used to select a clock source for 1-bit period in asynchronous mode or a detection method of the
start bit.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
ABCS — BRME
0 0 0 0
Description
(Valid only in asynchronous mode)
0: External clock input
1: Logical AND of two compare matches output from MTU
This bit is read as 0. The write value should be 0.
0: Bit rate modulation function is disabled.
1: Bit rate modulation function is enabled.
This bit is read as 0. The write value should be 0.
(Valid only in asynchronous mode)
0: Selects 16 base clock cycles for 1-bit period.
1: Selects 8 base clock cycles for 1-bit period.
(In asynchronous mode)
0: Noise cancellation function for the RXDn input signal is disabled.
1: Noise cancellation function for the RXDn input signal is enabled.
(in simple I
0: Noise cancellation function for the SSCLn and SSDAn input signals is
disabled.
1: Noise cancellation function for the SSCLn and SSDAn input signals is
enabled.
The NFEN bit should be 0 in any mode other than above.
(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode)
0: Baud rate generator outputs the clock with normal frequency.
1: Baud rate generator outputs the clock with doubled frequency.
(Valid only in asynchronous mode)
0: The low level on the RXDn pin is detected as the start bit.
1: A falling edge on the RXDn pin is detected as the start bit.
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
— ACS0
0 0
2
C mode)
R/W
1
R/W*
R/W
1
R/W*
R/W
1
R/W*
1
R/W*
1
R/W*
R/W* 1
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