Timer Output Control Register 1 (Tocr1A) - Renesas RX100 Series User Manual

RX13T Group
19.2.21

Timer Output Control Register 1 (TOCR1A)

Address(es): MTU.TOCR1A 0009 520Eh
b7 b6
— PSYE
Value after reset: 0 0
Bit Symbol Bit Name
b0 OLSP Output Level Select P*
b1 OLSN Output Level Select N*
b2 TOCS TOC Select
b3 TOCL TOC Register Write Protection
2, 4
* *
b5, b4 — Reserved
b6 PSYE PWM Synchronous Output Enable
b7 — Reserved
Note 1. Setting the TOCR1j.TOCS bit to 0 makes this bit setting valid.
Note 2. Setting the TOCR1j.TOCL bit to 1 prevents accidental modification when the CPU goes out of control.
Note 3. If dead-time is not generated, the negative-phase output is the exact inverse of the positive-phase output. In this case, only the
OLSP bit is valid.
Note 4. This bit can be set to 1 only once after a reset. After 1 is written, 0 cannot be written to the bit.
TOCR1A enables or disables PWM-synchronized toggle output in complementary PWM mode and reset-synchronized
PWM mode, and control inversion of PWM output level.
OLSP Bit (Output Level Select P)
This bit selects the positive-phase output level in reset-synchronized PWM mode and complementary PWM mode.
The initial output is selected while the counter is stopped.
OLSN Bit (Output Level Select N)
This bit selects the negative-phase output level in reset-synchronized PWM mode and complementary PWM mode.
The initial output is selected while the counter is stopped.
TOCS Bit (TOC Select)
This bit selects either the TOCR1j or TOCR2j (j = A) setting to be used for the output level in complementary PWM
mode and reset-synchronized PWM mode.
TOCL Bit (TOC Register Write Protection)
This bit enables or disables write access to the TOCS, OLSN, and OLSP bits in TOCR1j (j = A).
PSYE Bit (PWM Synchronous Output Enable)
This bit enables or disables toggle output synchronized with the PWM period.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — TOCL TOCS OLSN
0 0 0 0
Description
1, * 3 Refer to Table 19.30.
1, 3
* Refer to Table 19.31.
0: TOCR1j setting is selected (j = A)
1: TOCR2j setting is selected
0: Write access to the TOCS, OLSN, and OLSP bits is enabled
1: Write access to the TOCS, OLSN, and OLSP bits is disabled
These bits are read as 0. The write value should be 0.
0: Toggle output is disabled
1: Toggle output is enabled
This bit is read as 0. The write value should be 0.
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
OLSP
0 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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