Interrupt Skipping Function 2; Notes When Complementary Pwm Mode Output Protection Function Is Not Used; Notes Regarding Timer Counter (Mtu5.Tcnt) And Timer General Register (Mtu5.Tgr) - Renesas RX100 Series User Manual

RX13T Group
19.6.22

Interrupt Skipping Function 2

When interrupt skipping function 2 is in use and the difference between the values in MTU4.TADCORA and
MTU4.TADCORB is small, correct counting of the number skipped may not be possible, in which case requests for A/D
conversion will not be generated with the expected timing. The conditions listed below thus apply to these settings.
(1) When the number skipped is zero for skipping function 2
 The difference between the values in MTU4.TADCORA and MTU4.TADCORB must be at least four.
 The interval of comparison for MTU4.TADCORA must be at least four cycles of PCLKB (the updated value of
MTU4.TADCORA is set to the previous value plus or minus at least four).
 The interval of comparison for MTU4.TADCORB must be at least four cycles of PCLKB (the updated value of
MTU4.TADCORB is set to the previous value plus or minus at least four).
(2) When the number skipped is one or more for skipping function 2
 The difference between the values in MTU4.TADCORA and MTU4.TADCORB must be at least two.
 The interval of comparison for MTU4.TADCORB must be at least two cycles of PCLKB (the updated value of
MTU4.TADCORB is set to the previous value plus or minus at least two).
19.6.23 Notes When Complementary PWM Mode Output Protection Function is Not
Used
The complementary PWM mode output protection function is initially enabled. For details, refer to section 20, Port
Output Enable 3 (POE3C) .
19.6.24 Notes Regarding Timer Counter (MTU5.TCNT) and Timer General Register
(MTU5.TGR)
Do not set an MTU5.TGRj (j = U, V, W) bit to the value of the corresponding MTU5.TCNTj (j = U, V, W) plus one while
counting by the MTU5.TCNTj (j = U, V, W) register is stopped. If an MTU5.TGRj (j = U, V, W) bit is set to the value of
the corresponding MTU5.TCNTj (j = U, V, W) plus one while counting by the MTU5.TCNTj (j = U, V, W) is stopped, a
compare-match will be generated even though counting is stopped.
In this case, if the compare match enable bit (MTU5.TIER.TGIE5j (j = U, V, W) bit is set to 1 (enabling interrupts), a
compare-match interrupt will also be generated. If the value of the timer compare match clear register is 1 (enabled), the
timer is automatically cleared to 0000h when the compare-match is generated, regardless of whether interrupts from the
MTU5.TCNTj (j = U, V, W) are enabled or disabled.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
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