Renesas RX100 Series User Manual page 403

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(5) Cascaded Operation Example (d)

Figure 19.24 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE

bit has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the

IOA[3:0] bits in MTU1.TIOR have selected occurrence of MTU0.TGRA compare match or input capture for the input

capture timing while the IOA[3:0] bits in MTU2.TIOR have selected the MTIOC2A rising edge for the input capture

Under these conditions, as MTU1.TIOR has selected occurrence of MTU0.TGRA compare match or input capture for

the input capture timing, the MTIOC2A edge is not used for MTU1.TGRA input capture condition although the I2AE bit

in TICCR has been set to 1.

MTU0.TCNT value

MTU2.TCNT value

Figure 19.24

Cascaded Operation Example (d)

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

Compare match between MTU0.TCNT and MTU0.TGRA

19. Multi-Function Timer Pulse Unit 3 (MTU3c)

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