Renesas RX100 Series User Manual page 664

RX13T Group
Synchronization
clock
Serial data
RXI interrupt flag
1
(IRn in ICU* )
SSR.ORER flag
RXI interrupt
request
generated
RTSn# pin
Note 1. Refer to section 14, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.
Figure 23.29 Example of Operation for Serial Reception in Clock Synchronous Mode (2) (When RTS Function
is Used)
Data transfer cannot be resumed while a receive error flag is 1. Accordingly, clear the ORER, FER, and PER flags in the
SSR register to 0 before resuming reception. Moreover, be sure to read the RDR register during overrun error processing.
When a reception is forcibly terminated by setting the SCR.RE bit to 0 during operation, read the RDR register because
received data which has not yet been read may be left in the RDR register.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Bit 7 Bit 0
RDR data read in RXI
interrupt handling
routine
23. Serial Communications Interface (SCIg, SCIh)
Bit 6
Bit 7
RXI interrupt
request
generated
1 frame
Bit 0
RDR data read in RXI
interrupt handling routine
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