Cac Interrupt Request Enable Register (Caicr) - Renesas RX100 Series User Manual

RX13T Group
10.2.4

CAC Interrupt Request Enable Register (CAICR)

Address(es): 0008 B003h
b7 b6
OVFFC
—
L
Value after reset: 0 0
Bit Symbol
b0 FERRIE
b1 MENDIE
b2 OVFIE
b3 —
b4 FERRFCL
b5 MENDFCL
b6 OVFFCL
b7 —
FERRIE Bit (Frequency Error Interrupt Request Enable)
This bit specifies whether the frequency error interrupt request is enabled or disabled.
MENDIE Bit (Measurement End Interrupt Request Enable)
This bit specifies whether the measurement end interrupt request is enabled or disabled.
OVFIE Bit (Overflow Interrupt Request Enable)
This bit specifies whether the overflow interrupt request is enabled or disabled.
FERRFCL Bit (FERRF Clear)
Setting this bit to 1 clears the CASTR.FERRF flag.
MENDFCL Bit (MENDF Clear)
Setting this bit to 1 clears the CASTR.MENDF flag.
OVFFCL Bit (OVFF Clear)
Setting this bit to 1 clears the CASTR.OVFF flag.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
MENDF FERRF OVFIE MENDI
—
CL CL
0 0 0 0
Bit Name
Frequency Error Interrupt Request
Enable
Measurement End Interrupt
Request Enable
Overflow Interrupt Request Enable 0: Overflow interrupt request is disabled.
Reserved
FERRF Clear
MENDF Clear
OVFF Clear
Reserved
10. Clock Frequency Accuracy Measurement Circuit (CAC)
b1 b0
FERRI
E E
0 0
Description
0: Frequency error interrupt request is disabled.
1: Frequency error interrupt request is enabled.
0: Measurement end interrupt request is disabled.
1: Measurement end interrupt request is enabled.
1: Overflow interrupt request is enabled.
This bit is read as 0. The write value should be 0.
When 1 is written to this bit, the CASTR.FERRF flag is
cleared. This bit is read as 0.
When 1 is written to this bit, the CASTR.MENDF flag is
cleared. This bit is read as 0.
When 1 is written to this bit, the CASTR.OVFF flag is cleared.
This bit is read as 0.
This bit is read as 0. The write value should be 0.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Page 161 of 1041