Repeat Transfer Mode - Renesas RX100 Series User Manual

RX13T Group
16.4.4

Repeat Transfer Mode

This mode allows 1-byte, 1-word, or 1-longword data transfer on a single transfer request.
Specify either transfer source or transfer destination for the repeat area by the MRB.DTS bit. The transfer count can be
set to 1 to 256. When the specified-count transfer is completed, the initial value of the address register specified in the
transfer counter and the repeat area is restored and transfer is repeated. The other address register is incremented or
decremented continuously or remains unchanged.
When the transfer counter CRAL is decreased to 00h in repeat transfer mode, the CRAL value is updated to the value set
in the CRAH register. Thus the transfer counter does not become 00h, which disables an interrupt request to be generated
to the CPU when the MRB.DISEL bit is set to 0 (an interrupt request to the CPU is generated on completion of the
specified number of data transfers).
Table 16.7 lists the register functions in repeat transfer mode, and Figure 16.7 shows the memory map of repeat
transfer mode.
Table 16.7 Register Functions in Repeat Transfer Mode
Register Description
SAR Transfer source address
DAR Transfer destination
address
CRAH Retains initial value of
transfer counter
CRAL Transfer counter A
CRB Transfer counter B
Note 1. Write-back operation is skipped when the MRA.WBDIS bit is 1.
Note 2. Write-back operation is skipped when address is fixed.
SAR
Figure 16.7 Memory Map of Repeat Transfer Mode (Transfer Source: Repeat Area)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Value Written Back by Writing Transfer Information*
When CRAL ≠ 1
Increment/decrement/fixed*
Increment/decrement/fixed*
CRAH
CRAL – 1
Not updated
Transfer source data area
(set to repeat area)
Data 1
Data 2
Data 3
Data 4
When CRAL = 1
When the MRB.DTS Bit is 0
2
Increment/decrement/fixed*
2
DAR register initial value
CRAH
CRAH
Not updated
Transfer destination data area
Data 1
Transfer Data 2
Data 3
Data 4
Data 1
Data 2
Data 3
Data 4
16. Data Transfer Controller (DTCb)
1
When the MRB.DTS Bit is 1
2
SAR register initial value
Increment/decrement/fixed*
DAR
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