Interrupts; Interrupt Sources; Timing Of Compare Match Interrupt Generation - Renesas RX100 Series User Manual

RX13T Group
21.4

Interrupts

21.4.1

Interrupt Sources

The CMT has channels and each of them to which a different vector address is allocated has a compare match interrupt
(CMIn) (n = 0, 1). When a compare match interrupt occurs, the corresponding interrupt request is output.
When the interrupt request is used to generate a CPU interrupt, the priority of channels can be changed by the interrupt
controller settings. For details, see section 14, Interrupt Controller (ICUb) .
Table 21.2 CMT Interrupt Sources
Name Interrupt Sources
CMI0 Compare match in CMT0
CMI1 Compare match in CMT1
21.4.2

Timing of Compare Match Interrupt Generation

When the CMCNT counter and the CMCOR register match, a compare match interrupt (CMIn) (n = 0, 1) is generated.
A compare match signal is generated at the last state in which the values match (the timing when the CMCNT counter
updates the matched count value). That is, after a match between the CMCOR register and the CMCNT counter, the
compare match signal is not generated until the next the CMCNT counter input clock.
Figure 21.4 shows the timing of a compare match interrupt.
Figure 21.4 Timing of a Compare Match Interrupt
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
PCLK
CMCNT input clock
CMCNT
CMCOR
Compare match signal
Interrupt request
(edge)
DTC Activation
Possible
Possible
0
N
N
21. Compare Match Timer (CMT)
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