Dtc Transfer Count Register B (Crb); Dtc Control Register (Dtccr) - Renesas RX100 Series User Manual

RX13T Group
16.2.7

DTC Transfer Count Register B (CRB)

Address(es): (inaccessible directly from the CPU)
b15 b14
Value after reset: x x
x: Undefined
CRB register is used to set the block transfer count for block transfer mode and cannot be accessed directly from the
CPU.
The transfer count is 1, 65535, and 65536 when the set value is 0001h, FFFFh, and 0000h, respectively.
The CRB value is decremented (–1) when the final data of a single block size is transferred.
When normal transfer mode or repeat transfer mode is selected, this register is not used and the set value is ignored.
16.2.8

DTC Control Register (DTCCR)

Address(es): DTC.DTCCR 0008 2400h
b7 b6
— —
0 0
Value after reset:
Bit Symbol
b2 to b0 —
b3 —
b4 RRS
b7 to b5 —
Note 1. Set this bit to 0 when using the sequence transfer.
DTCCR register is used to control the DTC operation.
RRS Bit (DTC Transfer Information Read Skip Enable)
The DTC vector number is compared with the vector number in the previous data transfer.
When these vector numbers match and the RRS bit is set to 1, DTC data transfer is performed without reading the
transferred information. However, when the previous transfer was chain transfer, the transferred information is read
regardless of the value of the RRS bit.
Furthermore, when the transfer counter (CRA register) became 0 during the previous normal transfer and when the
transfer counter (CRB register) became 0 during the previous block transfer, the transferred information is read
regardless of the RRS bit value.
If the value of the MRA.WBDIS bit in any transfer information is 1, set the RRS bit to 0. Note that the MRA.WBDIS bit
should be set to 1 when the MRC.DISPE bit is set to 1.
Like chain transfer, sequence transfer handles sequences of multiple types of data transfer. When sequence transfer is to
be used, set the RRS bit to 0 so that the previous data transfer will not be repeated.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
x x x x
b5 b4 b3 b2
— RRS — —
0 0 1 0
Bit Name Description
Reserved These bits are read as 0. The write value should be 0.
Reserved This bit is read as 1. The write value should be 1.
DTC Transfer Information 0: Transfer information read is not skipped.
1
Read Skip Enable* 1: Transfer information read is skipped when vector numbers match.
Reserved These bits are read as 0. The write value should be 0.
b9 b8 b7 b6
x x x x
b1 b0
— —
0 0
16. Data Transfer Controller (DTCb)
b5 b4 b3 b2
x x x x
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b1 b0
x x
R/W
R/W
R/W
R/W
R/W