Renesas RX100 Series User Manual page 379

32-bit mcu
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RX13T Group
Table 19.41
Setting of Transfer Timing by TADCR.BF[1:0] Bits (MTU4)
Bit 15
Bit 14
Description
In Complementary PWM
BF[1]
BF[0]
Mode
0
0
Data is not transferred from
the cycle set buffer register
(MTU4.TADCOBRA,
MTU4.TADCOBRB) to the
cycle set register
(MTU4.TADCORA,
MTU4.TADCORB).
0
1
Data is transferred from the
cycle set buffer register
(MTU4.TADCOBRA,
MTU4.TADCOBRB) to the
cycle set register
(MTU4.TADCORA,
MTU4.TADCORB) at the
crest of the MTU4.TCNT.
1
0
Data is transferred from the
cycle set buffer register
(MTU4.TADCOBRA,
MTU4.TADCOBRB) to the
cycle set register
(MTU4.TADCORA,
MTU4.TADCORB) at the
trough of the MTU4.TCNT.
1
1
Data is transferred from the
cycle set buffer register
(MTU4.TADCOBRA,
MTU4.TADCOBRB) to the
cycle set register
(MTU4.TADCORA,
MTU4.TADCORB) at the
crest and trough of the
MTU4.TCNT.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
In Reset-Synchronized
PWM Mode
In PWM Mode 1
Data is not transferred from
Data is not transferred from
the cycle set buffer register
the cycle set buffer register
(MTU4.TADCOBRA,
(MTU4.TADCOBRA,
MTU4.TADCOBRB) to the
MTU4.TADCOBRB) to the
cycle set register
cycle set register
(MTU4.TADCORA,
(MTU4.TADCORA,
MTU4.TADCORB).
MTU4.TADCORB).
Data is transferred from the
Data is transferred from the
cycle set buffer register
cycle set buffer register
(MTU4.TADCOBRA,
(MTU4.TADCOBRA,
MTU4.TADCOBRB) to the
MTU4.TADCOBRB) to the
cycle set register
cycle set register
(MTU4.TADCORA,
(MTU4.TADCORA,
MTU4.TADCORB) when a
MTU4.TADCORB) when a
compare match occurs
compare match occurs
between MTU3.TCNT and
between MTU4.TCNT and
MTU3.TGRA.
MTU4.TGRA.
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
In Normal Mode
Data is not transferred from
the cycle set buffer register
(MTU4.TADCOBRA,
MTU4.TADCOBRB) to the
cycle set register
(MTU4.TADCORA,
MTU4.TADCORB).
Data is transferred from the
cycle set buffer register
(MTU4.TADCOBRA,
MTU4.TADCOBRB) to the
cycle set register
(MTU4.TADCORA,
MTU4.TADCORB) when a
compare match occurs
between MTU4.TCNT and
MTU4.TGRA.
Setting prohibited
Setting prohibited
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