Pwm Modes - Renesas RX100 Series User Manual

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PWM Modes

PWM modes are provided to output PWM waveforms from the external pins. The output level can be selected as low,

high, or toggle output in response to a compare match of each TGR.

PWM waveforms in the range of 0% to 100% duty cycle can be output according to the TGR settings.

By designating TGR compare match as the counter clearing source, the PWM period can be specified in that register.

Every channel except MTU5 can be set to PWM mode independently. Channels set to PWM mode can perform

synchronous operation with each other or other channels set to any other mode.

There are two PWM modes as described below.

(a) PWM Mode 1

PWM waveforms are output from the MTIOCnA and MTIOCnC pins by pairing TGRA with TGRB and TGRC with

TGRD. The levels specified by the TIOR.IOA[3:0] and IOC[3:0] bits are output from the MTIOCnA and MTIOCnC

pins at compare matches A and C, and the level specified by the TIOR.IOB[3:0] and IOD[3:0] bits are output at compare

matches B and D (n = 0 to 4). The initial output value is set in TGRA or TGRC. If the values set in paired TGRs are

identical, the output value does not change even when a compare match occurs.

In PWM mode 1, PWM waveforms in up to eight phases can be output.

(b) PWM Mode 2

PWM waveform output is generated using one TGR as the period register and the others as duty registers. The level

specified in TIOR is output at compare matches. Upon counter clearing by a period register compare match, the initial

value set in TIOR is output from each pin. If the values set in the period and duty registers are identical, the output value

does not change even when a compare match occurs.

Up to eight phases of PWM waveforms can be output by combining synchronous clearing of channels that cannot be set

to PWM mode 2 as synchronous operation.

The correspondence between PWM output pins and registers is shown in Table 19.49 .

PWM Output Registers and Output Pins

In PWM mode 2, PWM waveform output is not possible for the TGR register in which the PWM period is set.

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

19. Multi-Function Timer Pulse Unit 3 (MTU3c)

Setting prohibited

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