Renesas RX100 Series User Manual page 17

19.3.4 Cascaded Operation .................................................................................................................. 399
19.3.5 PWM Modes ............................................................................................................................. 404
19.3.6 Phase Counting Mode ............................................................................................................... 408
19.3.6.1 16-Bit Phase Counting Mode .......................................................................................... 408
19.3.6.2 Cascade Connection 32-Bit Phase Counting Mode ......................................................... 419
19.3.7 Reset-Synchronized PWM Mode ............................................................................................. 420
19.3.8 Complementary PWM Mode .................................................................................................... 423
19.3.9 A/D Converter Start Request Delaying Function ..................................................................... 458
19.3.10 Synchronous Operation of MTU0 to MTU4 ............................................................................ 464
19.3.11 External Pulse Width Measurement ......................................................................................... 465
19.3.12 Dead Time Compensation ........................................................................................................ 466
19.3.13 TCNTU, TCNTV, and TCNTW Capture at Crest and/or Trough
in Complementary PWM Mode ............................................................................................... 468
19.3.14 Noise Filter Function ................................................................................................................ 469
19.3.15 A/D Conversion Start Request Frame Synchronization Signal ................................................ 469
19.4 Interrupt Sources ................................................................................................................................ 470
19.4.1 Interrupt Sources and Priorities ................................................................................................ 470
19.4.2 DTC Trigger Sources ................................................................................................................ 471
19.4.3 A/D Converter Trigger Sources ................................................................................................ 472
19.5 Operation Timing .............................................................................................................................. 474
19.5.1 Input/Output Timing ................................................................................................................. 474
19.5.2 Interrupt Signal Timing ............................................................................................................ 480
19.6 Usage Notes ....................................................................................................................................... 483
19.6.1 Module Stop Function Setting .................................................................................................. 483
19.6.2 Count Clock Restrictions .......................................................................................................... 483
19.6.3 Note on Period Setting .............................................................................................................. 483
19.6.4 Contention between TCNT Write and Clear Operations .......................................................... 484
19.6.5 Contention between TCNT Write and Increment Operations .................................................. 484
19.6.6 Contention between TGR Write Operation and Compare Match ............................................ 485
19.6.7 Contention between Buffer Register Write Operation and Compare Match ............................ 485
19.6.8 Contention between Buffer Register Write and TCNT Clear Operations ................................ 486
19.6.9 Contention between TGR Read Operation and Input Capture ................................................. 486
19.6.10 Contention between TGR Write Operation and Input Capture ................................................ 487
19.6.11 Contention between Buffer Register Write Operation and Input Capture ............................... 488
19.6.12 Contention between MTU2.TCNT Write Operation and Overflow/Underflow
in Cascaded Operation .............................................................................................................. 489
19.6.13 Counter Value When Count Operation is Stopped in Complementary PWM Mode ............... 490
19.6.14 Buffer Operation Setting in Complementary PWM Mode ....................................................... 490
19.6.15 Buffer Operation and Compare Match in Reset-Synchronized PWM Mode ........................... 491
19.6.16 Overflow in Reset-Synchronized PWM Mode ......................................................................... 492
19.6.17 Contention between Overflow/Underflow and Counter Clearing ............................................ 493
19.6.18 Contention between TCNT Write Operation and Overflow/Underflow .................................. 493