23.11 Noise Cancellation Function - Renesas RX100 Series User Manual

RX13T Group

23.11 Noise Cancellation Function

Figure 23.74 shows the configuration of the noise filter used for noise cancellation. The noise filter consists of two
stages of flip-flop circuits and a match-detection circuit. When the level on the pin matches in three consecutive samples
taken at the set sampling interval, the matching level continues to be conveyed internally until the level on the pin again
matches in three consecutive samples.
In asynchronous mode, the noise cancellation function can be applied on the RXDn input signal. The period of the base
clock (1/16th of a bit-period when SEMR.ABCS = 0 and 1/8th of a bit-period when SEMR.ABCS = 1) is the sampling
interval.
2
In simple I C mode, the noise cancellation function can be applied on the SSDAn and SSCLn input signals. The
sampling clock is the clock signal produced by frequency-dividing the signal from the clock source for the internal baud-
rate generator by one, two, four, or eight as selected by the setting of the SNFR.NFCS[2:0] bits.
If the base clock is stopped with the noise filter enabled and then the clock input is started again, the noise filter operation
resumes from where the clock was stopped. If SCR.TE and SCR.RE are set to 0 during base clock input, all of the noise
filter flip-flop values are initialized to 1. Accordingly, if the input data is 1 when reception operation resumes, it is
determined that a level match is detected and is conveyed to the internal signal. When the level being input corresponds
to 0, the initial output of the noise filter is retained until the level matches in three consecutive samples.
TXDn/SSDAn,
RXDn/SSCLn
input signal
Clock source for the on-chip
baud rate generator
Base clock for
asynchronous mode
Figure 23.74 Block Diagram of Digital Noise Filter Circuit
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
D Q
Divided by 1 CLK
Divided by 2
Divided by 4
Divided by 8
NFCS[2:0] bits
23. Serial Communications Interface (SCIg, SCIh)
Not match
Match
Com-
parator
D Q
CLK
TXDn/SSDAn,
RXDn/SSCLn
internal signals
D Q
CLK
NFE bit
Page 710 of 1041