High-Impedance Control Using Registers; High-Impedance Control Through Detection Of Oscillation Stop; High-Impedance Control Through Detection Of The Comparator Output; Additional Functions For High-Impedance Control - Renesas RX100 Series User Manual

RX13T Group
20.3.3

High-Impedance Control Using Registers

The high-impedance request of the MTU pins (MTU0, MTU3, and MTU4) can be directly controlled by using the
SPOER register.
For instance, setting the SPOER.MTUCH34HIZ bit to 1 switches the MTU3 and MTU4 pins specified by the POECR2
register to the high-impedance state.
The high-impedance request of other pins can also be controlled by setting the appropriate bits in the SPOER register.
20.3.4

High-Impedance Control through Detection of Oscillation Stop

When oscillation stop is detected by the oscillation stop detection function of the clock generator while the
ICSR6.OSTSTE bit is 1, the MTU complementary PWM output pins specified by the POECR2 register and the MTU0
pins specified by the POECR1 register are switched to the high-impedance state.
20.3.5

High-Impedance Control through Detection of the Comparator Output

The outputs of the MTU complementary PWM output pins and MTU0 pins can be in the high-impedance state in
response to detection of the output from the comparator.
For instance, when the POECMPFR.CnFLAG flag (n = 0 to 2) is added to the high-impedance control conditions for the
MTU3 and MTU4 pins by setting the POECR4.CMADDMT34ZE bit to 1, the MTU3 and MTU4 pins specified by the
POECR2 register become high-impedance on comparator output detection.
The high-impedance control of other pins can be controlled by the POECR1 to POECR5 registers.
20.3.6

Additional Functions for High-Impedance Control

High-impedance control conditions for the MTU complementary PWM output pins, and MTU0 pins can be added by
setting the POECR4 and POECR5 registers.
For instance, the settings listed below can be added as high-impedance control conditions for the MTU3 and MTU4 pins.
 Setting the POECR4.CMADDMT34ZE bit to 1 adds comparator output detection
 Setting the POECR4.IC3ADDMT34ZE bit to 1 and adds the input-level detection by the POE8# pin
 Setting the POECR4.IC4ADDMT34ZE bit to 1 and adds the input-level detection by the POE10# pin
The high-impedance control of other pins can also be controlled by setting the appropriate bits in the POECR4 and
POECR5 registers.
20.3.7

Recover from High-Impedance State

The outputs which have been in the high-impedance state due to input-level detection can be recovered from the state
either by returning them to their initial state with a reset, or by clearing all of the ICSR1.POE0F, ICSR3.POE8F, and
ICSR4.POE10F flags. However, note that when low-level sampling is selected with the ICSR1.POE0M[1:0],
ICSR3.POE8M[1:0], and ICSR4.POE10M[1:0] bits, just writing 0 to a flag is ignored (the flag is not set to 0); flags can
be cleared by writing 0 to it only after a high level is input to the POE0#, POE8#, and POE10# pins and is detected.
The outputs which have been in the high-impedance state due to output-level detection can be recovered from the state
either by returning them to their initial state with a reset, or by setting the OCSR1.OSF1 flag to 0. However, note that just
writing 0 to a flag is ignored (the flag is not set to 0); the flags can be cleared by writing 0 to it only after setting the
inactive level to be output from the pin. In the MTU, the inactive level (initial output level) can be output by stopping the
count operation.
The outputs which have been in the high-impedance state due to comparator output detection can be recovered from the
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
20. Port Output Enable 3 (POE3C)
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