Renesas RX100 Series User Manual page 593

RX13T Group
(2) Smart Card Interface Mode (SCMR.SMIF = 1)
Address(es): SMCI1.SMR 0008 A020h, SMCI5.SMR 0008 A0A0h, SMCI12.SMR 0008 B300h
b7 b6
GM BLK
0 0
Value after reset:
Bit Symbol Bit Name
b1, b0 CKS[1:0] Clock Select
b3, b2 BCP[1:0] Base Clock Pulse
b4 PM Parity Mode
b5 PE Parity Enable
b6 BLK Block Transfer
Mode
b7 GM GSM Mode
Note 1. n is the decimal notation of the value of n in BRR (refer to section 23.2.11, Bit Rate Register (BRR)).
Note 2. Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
CKS[1:0] Bits (Clock Select)
These bits select the clock source for the on-chip baud rate generator.
For the relationship between the settings of these bits and the baud rate, refer to section 23.2.11, Bit Rate Register
(BRR) .
BCP[1:0] Bits (Base Clock Pulse)
These bits select the number of base clock cycles in a 1-bit data transfer time in smart card interface mode.
Set these bits in combination with the SCMR.BCP2 bit.
For details, refer to section 23.6.4, Receive Data Sampling Timing and Reception Margin .
Table 23.8 Combinations of the SCMR.BCP2 Bit and SMR.BCP[1:0] Bits
SCMR.BCP2 Bit SMR.BCP[1:0] Bits
0
0
0
0
1
1
1
1
Note 1. S is the value of S in BRR (refer to section 23.2.11, Bit Rate Register (BRR)).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
PE PM BCP[1:0]
0 0 0 0
Description
b1 b0
0 0: PCLK (n = 0)*
0 1: PCLK/4 (n = 1)*
1 0: PCLK/16 (n = 2)*
1 1: PCLK/64 (n = 3)*
Selects the number of base clock cycles in combination with the SCMR.BCP2
bit.
Table 23.8 lists the combinations of the SCMR.BCP2 bit and SMR.BCP[1:0] bits.
(Valid only when the PE bit is 1)
0: Selects even parity
1: Selects odd parity
When this bit is set to 1, a parity bit is added to transmit data, and the parity of
received data is checked. Set this bit to 1 in smart card interface mode.
0: Non-block transfer mode operation
1: Block transfer mode operation
0: Non-GSM mode operation
1: GSM mode operation
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
CKS[1:0]
0 0
1
1
1
1
Number of Base Clock Cycles for 1-Bit Transfer Period
93 clock cycles (S = 93)*
128 clock cycles (S = 128)*
186 clock cycles (S = 186)*
512 clock cycles (S = 512)*
32 clock cycles (S = 32)*
64 clock cycles (S = 64)*
372 clock cycles (S = 372)*
256 clock cycles (S = 256)*
1
1
1
1
1
(Initial Value)
1
1
1
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