Independent Watchdog Timer Reset; Software Reset - Renesas RX100 Series User Manual

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External voltage

LVCMPCR.LVDiE

LVDiCR0.LVDiRN = 0

Voltage detection i

signal (Low is valid)

RSTSR0.LVDiRF

Internal reset signal

LVDiCR0.LVDiRN = 1

Voltage detection i

signal (Low is valid)

RSTSR0.LVDiRF

Internal reset signal

For details on the electrical characteristics, see the Electrical Characteristics section.

Note 1. Vdeti shows a detection level of voltage monitoring 1 reset and voltage monitoring 2 reset. (i = 1, 2)

Note 2. tLVDi shows a time for voltage monitoring 1 reset and voltage monitoring 2 reset. (i = 1, 2)

Operation Examples During Voltage Monitoring 1 Reset and Voltage Monitoring 2 Reset

Independent Watchdog Timer Reset

Independent watchdog timer reset is an internal reset generated by the independent watchdog timer.

Output of the independent watchdog timer reset from the independent watchdog timer can be selected by setting the

IWDT reset control register (IWDTRCR) and option function select register 0 (OFS0).

When output of the independent watchdog timer reset is selected, an independent watchdog timer reset is generated if the

independent watchdog timer underflows, or if data is written outside the refresh-permitted period. When the internal

reset time (tRESW2) has elapsed after the independent watchdog timer reset has been generated, the internal reset is

canceled and the CPU starts the reset exception handling.

For details on the independent watchdog timer reset, see section 22, Independent Watchdog Timer (IWDTa) .

The software reset is an internal reset generated by the software reset circuit.

When A501h is written to SWRR, a software reset is generated. When the internal reset time (tRESW2) has elapsed after

the software reset is generated, the internal reset is canceled and the CPU starts the reset exception handling.

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

LVDi valid setting

RES# pin reset

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