Timer General Register (Tgr); Timer Longword General Registers (Tgralw, Tgrblw) - Renesas RX100 Series User Manual

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Timer General Register (TGR)

Address(es): MTU0.TGRA 0009 5308h, MTU0.TGRB 0009 530Ah, MTU0.TGRC 0009 530Ch, MTU0.TGRD 0009 530Eh, MTU0.TGRE 0009 5320h,

MTU0.TGRF 0009 5322h,

MTU1.TGRA 0009 5388h, MTU1.TGRB 0009 538Ah,

MTU2.TGRA 0009 5408h, MTU2.TGRB 0009 540Ah,

MTU3.TGRA 0009 5218h, MTU3.TGRB 0009 521Ah, MTU3.TGRC 0009 5224h, MTU3.TGRD 0009 5226h, MTU3.TGRE 0009 5272h,

MTU4.TGRA 0009 521Ch, MTU4.TGRB 0009 521Eh, MTU4.TGRC 0009 5228h, MTU4.TGRD 0009 522Ah, MTU4.TGRE 0009 5274h,

MTU4.TGRF 0009 5276h,

MTU5.TGRU 0009 5482h, MTU5.TGRV 0009 5492h, MTU5.TGRW 0009 54A2h

Value after reset:

TGR must not be accessed in 8 bits; it should be accessed in 16 bits. The initial value of TGR is FFFFh.

The TGR register is 16-bit readable/writable register. The MTU has a total of 24 TGR registers, six for MTU0, two each

for MTU1 and MTU2, five for MTU3, six for MTU4, and three for MTU5.

The TGRA, TGRB, TGRC, and TGRD registers function as either output compare or input capture registers. The TGRC

and TGRD registers for MTU0, MTU3, and MTU4 can also be designated for operation as buffer registers. TGR buffer

MTU0.TGRE and MTU0.TGRF function as compare registers. When the MTU0.TCNT count matches the

MTU0.TGRE value, an A/D converter start request can be issued. The TGRF register can also be designated for

operation as a buffer register. TGR buffer register combination is TGRE and TGRF. MTU5.TGRU, MTU5.TGRV, and

MTU5.TGRW function as compare match, input capture, or external pulse width measurement registers.

The MTU1.TGRA, MTU2.TGRA, MTU1.TGRB, and MTU2.TGRB registers are read as 0000h when TMDR3.LWA is

1. Refer to section 19.2.5, Timer Mode Register 3 (TMDR3) for details.

Address(es): MTU1.TGRALW 0009 53A4h, MTU1.TGRBLW 0009 53A8h

Value after reset:

Value after reset:

TGRALW and TGRBLW must not be accessed in 8 or 16 bits; it should be accessed in 32 bits.

The TGRnLW register (n = A, B) is a 32-bit readable/writable register. Two general registers of this type are provided,

and are formed by combining MTU1.TGRn and MTU2.TGRn. Such operation is only effective when TMDR3.LWA is 1.

The TGRnLW register is initialized to FFFF FFFFh by a reset, but it is read as 0000 0000h when TMDR3.LWA is 0.

Refer to section 19.2.5, Timer Mode Register 3 (TMDR3) for details.

The TGRnLW register functions as an output compare or input capture register when TMDR3.LWA is 1.

This register can only be used in 32-bit phase counting mode.

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

19. Multi-Function Timer Pulse Unit 3 (MTU3c)

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