Register Descriptions; Dtc Mode Register A (Mra) - Renesas RX100 Series User Manual

RX13T Group
16.2

Register Descriptions

Registers MRA, MRB, MRC, SAR, DAR, CRA, and CRB are DTC internal registers, which cannot be directly accessed
from the CPU. Values to be set in these DTC internal registers are placed in the RAM area as transfer information. When
accepting a transfer request, the DTC reads the transfer information from the RAM area and sets it in the internal
registers. After the data transfer ends, the values of the updated internal register are written back to the RAM area as
transfer information.
16.2.1

DTC Mode Register A (MRA)

Address(es): (inaccessible directly from the CPU)
b7 b6
MD[1:0]
Value after reset: x x
x: Undefined
Bit Symbol Bit Name
b0 WBDIS Write-back Disable
b1 — Reserved
b3, b2 SM[1:0] Transfer Source Address Addressing
Mode
b5, b4 SZ[1:0] DTC Data Transfer Size
b7, b6 MD[1:0] DTC Transfer Mode Select
MRA register is used to select the DTC operating mode and cannot be accessed directly from the CPU.
WBDIS Bit (Write-back Disable)
The WBDIS bit selects whether to write back the transfer information.
When the bit is 0, updated transfer information is written back.
When the bit is 1, updated transfer information is not written back even with the setting of that address is incremented
after a transfer, and the same data transfer is executed every time for each transfer request. The transfer information can
be stored in ROM because the transfer information is not written back.
While the WBDIS bit is 1, operation for each transfer mode is as follows:
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
SZ[1:0] SM[1:0]
x x x x
b1 b0
— WBDIS
x x
Description
0: Writes back the transfer information on completion of the
data transfer
1: Does not write back the transfer information on completion
of the data transfer
Set this bit to 0.
b3 b2
0 0: The address in the SAR register is fixed.
(write-back to SAR is skipped.)
0 1: The address in the SAR register is fixed.
(write-back to SAR is skipped.)
1 0: The SAR value is incremented after a data transfer.
(+1 when the SZ[1:0] bits are 00b, +2 when 01b, +4
when 10b)
1 1: The SAR value is decremented after a data transfer.
(–1 when the SZ[1:0] bits are 00b, –2 when 01b, –4
when 10b)
b5 b4
0 0: Byte (8-bit) transfer
0 1: Word (16-bit) transfer
1 0: Longword (32-bit) transfer
1 1: Setting prohibited
b7 b6
0 0: Normal transfer mode
0 1: Repeat transfer mode
1 0: Block transfer mode
1 1: Setting prohibited
16. Data Transfer Controller (DTCb)
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