Compare Match Counter (Cmcnt); Compare Match Constant Register (Cmcor) - Renesas RX100 Series User Manual

32-bit mcu
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21.2.3

Compare Match Counter (CMCNT)

Address(es): CMT0.CMCNT 0008 8004h, CMT1.CMCNT 0008 800Ah
b15
b14
0
0
Value after reset:
The CMCNT counter is a readable/writable up-counter.
When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTR0.STRn (n = 0, 1) bit is set to
1, the CMCNT counter starts counting up using the selected clock.
When the value in the CMCNT counter and the value in the CMCOR register match, the CMCNT counter is set to
0000h. At the same time, a compare match interrupt (CMIn) (n = 0, 1) is generated.
21.2.4

Compare Match Constant Register (CMCOR)

Address(es): CMT0.CMCOR 0008 8006h, CMT1.CMCOR 0008 800Ch
b15
b14
Value after reset:
1
1
The CMCOR register is a readable/writable register to set a value for compare match with the CMCNT counter.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13
b12
b11
b10
0
0
0
0
b13
b12
b11
b10
1
1
1
1
b9
b8
b7
b6
0
0
0
0
b9
b8
b7
b6
1
1
1
1
21. Compare Match Timer (CMT)
b5
b4
b3
b2
0
0
0
0
b5
b4
b3
b2
1
1
1
1
Page 559 of 1041
b1
b0
0
0
b1
b0
1
1

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