Renesas RX100 Series User Manual page 9

7.2.1 Option Function Select Register 0 (OFS0) ............................................................................... 107
7.2.2 Option Function Select Register 1 (OFS1) ............................................................................... 109
7.2.3 Endian Select Register (MDE) ................................................................................................. 110
7.3 Usage Note ........................................................................................................................................ 111
7.3.1 Setting Example of Option-Setting Memory ............................................................................ 111
8. Voltage Detection Circuit (LVDAb) ............................................................................................... 112
8.1 Overview ........................................................................................................................................... 112
8.2 Register Descriptions ......................................................................................................................... 115
8.2.1 Voltage Monitoring 1 Circuit Control Register 1 (LVD1CR1) ............................................... 115
8.2.2 Voltage Monitoring 1 Circuit Status Register (LVD1SR) ....................................................... 116
8.2.3 Voltage Monitoring 2 Circuit Control Register 1 (LVD2CR1) ............................................... 117
8.2.4 Voltage Monitoring 2 Circuit Status Register (LVD2SR) ....................................................... 118
8.2.5 Voltage Monitoring Circuit Control Register (LVCMPCR) .................................................... 119
8.2.6 Voltage Detection Level Select Register (LVDLVLR) ........................................................... 120
8.2.7 Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0) ............................................... 121
8.2.8 Voltage Monitoring 2 Circuit Control Register 0 (LVD2CR0) ............................................... 122
8.3 VCC Input Voltage Monitor .............................................................................................................. 123
8.3.1 Monitoring Vdet0 ..................................................................................................................... 123
8.3.2 Monitoring Vdet1 ..................................................................................................................... 123
8.3.3 Monitoring Vdet2 ..................................................................................................................... 123
8.4 Reset from Voltage Monitor 0 ........................................................................................................... 124
8.5 Interrupt and Reset from Voltage Monitoring 1 ................................................................................ 125
8.6 Interrupt and Reset from Voltage Monitoring 2 ................................................................................ 127
9. Clock Generation Circuit .............................................................................................................. 129
9.1 Overview ........................................................................................................................................... 129
9.2 Register Descriptions ......................................................................................................................... 131
9.2.1 System Clock Control Register (SCKCR) ................................................................................ 131
9.2.2 System Clock Control Register 3 (SCKCR3) ........................................................................... 133
9.2.3 PLL Control Register (PLLCR) ............................................................................................... 134
9.2.4 PLL Control Register 2 (PLLCR2) .......................................................................................... 135
9.2.5 Main Clock Oscillator Control Register (MOSCCR) ............................................................... 136
9.2.6 Low-Speed On-Chip Oscillator Control Register (LOCOCR) ................................................. 137
9.2.7 IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR) ...................................... 138
9.2.8 High-Speed On-Chip Oscillator Control Register (HOCOCR) ............................................... 139
9.2.9 Oscillation Stabilization Flag Register (OSCOVFSR) ............................................................. 140
9.2.10 Oscillation Stop Detection Control Register (OSTDCR) ......................................................... 142
9.2.11 Oscillation Stop Detection Status Register (OSTDSR) ............................................................ 143
9.2.12 Main Clock Oscillator Wait Control Register (MOSCWTCR) ................................................ 144
9.2.13 Main Clock Oscillator Forced Oscillation Control Register (MOFCR) ................................... 145
9.2.14 Low-Speed On-Chip Oscillator Trimming Register (LOCOTRR) .......................................... 146
9.2.15 IWDT-Dedicated On-Chip Oscillator Trimming Register (ILOCOTRR) ............................... 146