Digital Filtering Of Signals On The Cacref Pin; Interrupt Requests - Renesas RX100 Series User Manual

RX13T Group
clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. Also, the
MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt is generated.
(5) When the next valid edge is input, the counter value is transferred in CACNTBR and compared with the values of
CAULVR and CALLVR. In the case of CACNTBR < CALLVR, the FERRF flag in CASTR is set to 1 because the
clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. Also, the
MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt is generated.
(6) While the CFME bit in CACR0 is 1, the counter value is transferred in CACNTBR and compared with the values of
CAULVR and CALLVR every time a valid edge is input. Writing 0 to the CFME bit in CACR0 clears the counter
and stops up-counting.
10.3.2

Digital Filtering of Signals on the CACREF Pin

The CACREF pin has a digital filter. Levels on the target pin for sampling are conveyed to the internal circuitry after
matching three consecutive times at the selected sampling interval and the same level continues to be conveyed internally
until the level on the pin again matches three consecutive times.
Enabling and disabling of the digital filter and its sampling clock are selectable.
The counter value transferred in CACNTBR may be in error by up to one cycle of the sampling clock due to the
difference between the phases of the digital filter and the signal input to the CACREF pin.
When a frequency dividing clock is selected as a count source clock, the counter value error is obtained by the following
formula:
Counter value error = (One cycle of the count source clock) / (One cycle of the sampling clock)
10.4

Interrupt Requests

The CAC generates three types of interrupt request: frequency error interrupt, measurement end interrupt, and overflow
interrupt. When an interrupt source is generated, the corresponding status flag becomes 1. Table 10.3 lists details on the
interrupt requests of the clock frequency accuracy measurement circuit.
Table 10.3 Interrupt Requests of Clock Frequency Accuracy Measurement Circuit
Interrupt Request Interrupt Enable Bit
Frequency error CAICR.FERRIE
interrupt
Measurement end CAICR.MENDIE
interrupt
Overflow interrupt CAICR.OVFIE
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
10. Clock Frequency Accuracy Measurement Circuit (CAC)
Status Flag Interrupt Source
CASTR.FERRF The result of comparing CACNTBR to CAULVR and CALLVR is
either CACNTBR > CAULVR or CACNTBR < CALLVR.
CASTR.MENDF A valid edge is input from the CACREF pin.
Note however that a measurement end interrupt does not occur
at the first valid edge after writing 1 to the CACR0.CFME bit.
CASTR.OVFF The counter has overflowed.
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